55 lines
2.0 KiB
LLVM
55 lines
2.0 KiB
LLVM
; RUN: opt -loop-vectorize -force-vector-width=1 -force-vector-interleave=2 \
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; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -S -o - < %s | FileCheck %s
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; RUN: opt -mattr=+sve -loop-vectorize -force-vector-width=1 -force-vector-interleave=2 \
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; RUN: -prefer-predicate-over-epilogue=scalar-epilogue -S -o - < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; This test is defending against a bug that appeared when we have a target
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; configuration where masked loads/stores are legal -- e.g. AArch64 with SVE.
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; Predication would not be applied during interleaving, enabling the
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; possibility of superfluous loads/stores which could result in miscompiles.
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; This test checks that, when we disable vectorisation and force interleaving,
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; stores are predicated properly.
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;
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; This is _not_ an SVE-specific test. The same bug could manifest on any
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; architecture with masked loads/stores, but we use SVE for testing purposes
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; here.
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define void @foo(i32* %data1, i32* %data2) {
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; CHECK-LABEL: @foo(
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; CHECK: vector.body:
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; CHECK: br i1 {{%.*}}, label %pred.store.if, label %pred.store.continue
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; CHECK: pred.store.if:
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; CHECK-NEXT: store i32 {{%.*}}, i32* {{%.*}}
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; CHECK-NEXT: br label %pred.store.continue
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; CHECK: pred.store.continue:
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; CHECK-NEXT: br i1 {{%.*}}, label %pred.store.if2, label %pred.store.continue3
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; CHECK: pred.store.if2:
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; CHECK-NEXT: store i32 {{%.*}}, i32* {{%.*}}
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; CHECK-NEXT: br label %pred.store.continue3
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; CHECK: pred.store.continue3:
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entry:
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br label %while.body
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while.body:
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%i = phi i64 [ 1023, %entry ], [ %i.next, %if.end ]
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%arrayidx = getelementptr inbounds i32, i32* %data1, i64 %i
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%ld = load i32, i32* %arrayidx, align 4
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%cmp = icmp sgt i32 %ld, %ld
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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store i32 %ld, i32* %arrayidx, align 4
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br label %if.end
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if.end:
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%i.next = add nsw i64 %i, -1
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%tobool.not = icmp eq i64 %i, 0
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br i1 %tobool.not, label %while.end, label %while.body
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while.end:
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ret void
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}
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