OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Thumb2/LowOverheadLoops
History
David Green 73346f5848 [ARM] Introduce a MQPRCopy 
Currently when creating tail predicated loops, we need to validate that
all the live-outs of a loop will be equivalent with and without tail
predication, and if they are not we cannot legally create a
tail-predicated loop, leaving expensive vctp and vpst instructions in
the loop. These notably can include register-allocation instructions
like stack loads and stores, and copys lowered from COPYs to MVE_VORRs.

Instead of trying to prove this is valid late in the pipeline, this
patch introduces a MQPRCopy pseudo instruction that COPY is lowered to.
This can then either be converted to a MVE_VORR where possible, or to a
couple of VMOVD instructions if not. This way they do not behave
differently within and outside of tail-predications regions, and we can
know by construction that they are always valid. The idea is that we can
do the same with stack load and stores, converting them to VLDR/VSTR or
VLDM/VSTM where required to prove tail predication is always valid.

This does unfortunately mean inserting multiple VMOVD instructions,
instead of a single MVE_VORR, but my experiments show it to be an
improvement in general.

Differential Revision: https://reviews.llvm.org/D111048
 		2021-10-07 12:52:12 +01:00
..
add_reduce.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
begin-vpt-without-inst.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
biquad-cascade-default.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
biquad-cascade-optsize-strd-lr.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
biquad-cascade-optsize.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
branch-targets.ll [ARM] Improve WLS lowering 2021-03-11 17:56:19 +00:00
clear-maskedinsts.ll
…
cmplx_cong.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
cond-mov.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
cond-vector-reduce-mve-codegen.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
constbound.ll [ARM] Remove DLS lr, lr 2021-02-02 11:09:31 +00:00
count_dominates_start.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
ctlz-non-zeros.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
disjoint-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
dont-ignore-vctp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
dont-remove-loop-update.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
emptyblock.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
end-positive-offset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
exitcount.ll [ARM] Remove dead mov's in preheader of tail predicated loops 2021-02-11 10:48:20 +00:00
extending-loads.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
extract-element.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
fast-fp-loops.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
incorrect-sub-8.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
incorrect-sub-16.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
incorrect-sub-32.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inlineasm.ll
…
inloop-vpnot-1.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpnot-2.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpnot-3.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpsel-1.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
inloop-vpsel-2.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
invariant-qreg.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-chain-store.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-chain.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-itercount.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-mov.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
it-block-random.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
iv-two-vcmp-reordered.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
iv-two-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
iv-vcmp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
livereg-no-loop-def.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
loop-dec-copy-chain.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
loop-dec-copy-prev-iteration.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
loop-dec-liveout.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
loop-guards.ll [ARM] Move t2DoLoopStart reg alloc hint 2021-03-11 17:56:19 +00:00
lsr-profitable-chain.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
lstp-insertion-position.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
massive.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
matrix-debug.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
matrix.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
memcall.ll [ARM] Introduce t2WhileLoopStartTP 2021-06-13 13:55:34 +01:00
minloop.ll [ARM] Remove DLS lr, lr 2021-02-02 11:09:31 +00:00
mov-after-dls.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
mov-after-dlstp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mov-lr-terminator.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mov-operand.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
move-def-before-start.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
move-start-after-def.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
multi-block-cond-iter-count.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
multi-cond-iter-count.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
multiblock-massive.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
multiple-do-loops.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
mve-float-loops.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
mve-tail-data-types.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
nested.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
no-dec-cbnz.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
no-dec-le-simple.ll
…
no-dec-reorder.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
no-dec.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
no-vpsel-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
non-masked-load.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
non-masked-store.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
out-of-range-cbz.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
predicated-invariant.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
predicated-liveout-unknown-lanes.ll [ARM] Generate VDUP(Const) from constant buildvectors 2021-06-08 20:51:33 +01:00
predicated-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
reductions-vpt-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
reductions.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
remat-vctp.ll [ARM] Ensure instructions are simplified prior to GatherScatter lowering. 2021-06-10 20:18:12 +01:00
remove-elem-moves.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
revert-after-call.mir
…
revert-after-read.mir
…
revert-after-write.mir
…
revert-non-header.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
revert-non-loop.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
revert-while.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
revertcallearly.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
safe-def-no-mov.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
safe-retaining.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
sibling-loops.ll
…
size-limit.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
skip-debug.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
skip-vpt-debug.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
spillingmove.ll [ARM] Introduce a MQPRCopy 2021-10-07 12:52:12 +01:00
spillingmove.mir [ARM] Introduce a MQPRCopy 2021-10-07 12:52:12 +01:00
subreg-liveness.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
switch.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
tail-pred-basic.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-const.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-disabled-in-loloops.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
tail-pred-intrinsic-add-sat.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-intrinsic-fabs.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-intrinsic-round.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
tail-pred-intrinsic-sub-sat.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-narrow.ll
…
tail-pred-pattern-fail.ll
…
tail-pred-reduce.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tail-pred-widen.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
tp-multiple-vpst.ll
…
unpredicated-max.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
unpredload.ll [ARM] Enable subreg liveness 2021-08-17 14:10:33 +01:00
unrolled-and-vector.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
unsafe-cpsr-loop-def.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unsafe-cpsr-loop-use.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
unsafe-retaining.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
unsafe-use-after.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
vaddv.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
varying-outer-2d-reduction.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
vcmp-vpst-combination-across-blocks.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vcmp-vpst-combination.ll
…
vctp-add-operand-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-in-vpt-2.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-in-vpt.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-subi3.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-subri.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp-subri12.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vctp16-reduce.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vector-arith-codegen.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
vector-reduce-mve-tail.ll [ARM] Clean up some tests, removing dead instructions. NFC 2021-05-22 13:38:00 +01:00
vector-unroll.ll
…
vector_spill_in_loop.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vmaxmin_vpred_r.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vmldava_in_vpt.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
vpt-block-debug.mir [ARM] Skip debug info in recomputeVPTBlockMask 2021-09-28 14:58:13 +01:00
vpt-blocks.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
while-loops.ll Revert "Allow rematerialization of virtual reg uses" 2021-09-24 10:26:11 -07:00
while-negative-offset.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
while.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wls-revert-placement.mir [ARM] Delay reverting WLS in arm-block-placement 2021-09-28 15:38:29 +01:00
wls-search-killed.mir CodeGen: Print/parse LLTs in MachineMemOperands 2021-06-30 16:54:13 -04:00
wls-search-pred.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wlstp.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wrong-liveout-lsr-shift.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wrong-vctp-opcode-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00
wrong-vctp-operand-liveout.mir [ARM] Add a tail-predication loop predicate register 2021-09-02 13:42:58 +01:00