123 lines
3.8 KiB
LLVM
123 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -basicaa -newgvn -S | FileCheck %s
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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define i1 @patatino(i8* %blah, i32 %choice) {
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; CHECK-LABEL: @patatino(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[WHILE_COND:%.*]]
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; CHECK: while.cond:
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; CHECK-NEXT: [[FOO:%.*]] = phi i8* [ [[BLAH:%.*]], [[ENTRY:%.*]] ], [ null, [[WHILE_BODY:%.*]] ]
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; CHECK-NEXT: switch i32 [[CHOICE:%.*]], label [[WHILE_BODY]] [
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; CHECK-NEXT: i32 -1, label [[WHILE_END:%.*]]
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; CHECK-NEXT: i32 40, label [[LAND_END:%.*]]
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; CHECK-NEXT: ]
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; CHECK: land.end:
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; CHECK-NEXT: br label [[WHILE_END]]
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; CHECK: while.body:
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; CHECK-NEXT: br label [[WHILE_COND]]
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; CHECK: while.end:
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; CHECK-NEXT: store i8 0, i8* [[FOO]], align 1
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; CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* [[BLAH]], align 1
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; CHECK-NEXT: [[LOADED:%.*]] = icmp eq i8 [[TMP0]], 0
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; CHECK-NEXT: store i8 0, i8* [[BLAH]], align 1
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; CHECK-NEXT: ret i1 [[LOADED]]
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;
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entry:
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br label %while.cond
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while.cond:
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%foo = phi i8* [ %blah, %entry ], [ null, %while.body ]
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switch i32 %choice, label %while.body [
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i32 -1, label %while.end
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i32 40, label %land.end
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]
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land.end:
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br label %while.end
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while.body:
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br label %while.cond
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while.end:
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%foo.lcssa = phi i8* [ %foo, %land.end ], [ %foo, %while.cond ]
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;; These two stores will initially be considered equivalent, but then proven not.
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;; the second store would previously end up deciding it's equivalent to a previous
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;; store, but it was really just finding an optimistic version of itself
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;; in the congruence class.
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store i8 0, i8* %foo.lcssa, align 1
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%0 = load i8, i8* %blah, align 1
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%loaded = icmp eq i8 %0, 0
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store i8 0, i8* %blah, align 1
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ret i1 %loaded
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}
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;; This is an example of a case where the memory states are equivalent solely due to unreachability,
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;; but the stores are not equal.
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define void @foo(i8* %arg) {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[TMP:%.*]] = phi i8* [ [[ARG:%.*]], [[BB:%.*]] ], [ null, [[BB2:%.*]] ]
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; CHECK-NEXT: br i1 undef, label [[BB3:%.*]], label [[BB2]]
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; CHECK: bb2:
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; CHECK-NEXT: br label [[BB1]]
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; CHECK: bb3:
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; CHECK-NEXT: store i8 0, i8* [[TMP]], !g !0
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; CHECK-NEXT: br label [[BB4:%.*]]
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; CHECK: bb4:
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; CHECK-NEXT: br label [[BB6:%.*]]
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; CHECK: bb6:
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; CHECK-NEXT: br i1 undef, label [[BB9:%.*]], label [[BB7:%.*]]
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; CHECK: bb7:
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; CHECK-NEXT: switch i8 0, label [[BB6]] [
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; CHECK-NEXT: i8 6, label [[BB8:%.*]]
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; CHECK-NEXT: ]
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; CHECK: bb8:
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; CHECK-NEXT: store i8 undef, i8* null
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; CHECK-NEXT: br label [[BB4]]
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; CHECK: bb9:
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; CHECK-NEXT: store i8 0, i8* [[ARG]], !g !0
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; CHECK-NEXT: unreachable
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;
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bb:
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br label %bb1
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bb1: ; preds = %bb2, %bb
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%tmp = phi i8* [ %arg, %bb ], [ null, %bb2 ]
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br i1 undef, label %bb3, label %bb2
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bb2: ; preds = %bb1
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br label %bb1
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bb3: ; preds = %bb1
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store i8 0, i8* %tmp, !g !0
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br label %bb4
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bb4: ; preds = %bb8, %bb3
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%tmp5 = phi i8* [ null, %bb8 ], [ %arg, %bb3 ]
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br label %bb6
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bb6: ; preds = %bb7, %bb4
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br i1 undef, label %bb9, label %bb7
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bb7: ; preds = %bb6
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switch i8 0, label %bb6 [
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i8 6, label %bb8
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]
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bb8: ; preds = %bb7
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store i8 undef, i8* %tmp5, !g !0
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br label %bb4
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bb9: ; preds = %bb6
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%tmp10 = phi i8* [ %tmp5, %bb6 ]
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store i8 0, i8* %tmp10, !g !0
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unreachable
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}
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!0 = !{}
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