Andrea Di Biagio 815cdbff29 [X86][Btver2] Improved latency/throughput model for scalar int-to-float conversions. ... Account for bypass delays when computing the latency of scalar int-to-float conversions. On Jaguar we need to account for an extra 6cy latency (see AMD fam16h SOG). This patch also fixes the number of micropcodes for the register-memory variants of scalar int-to-float conversions. Differential Revision: https://reviews.llvm.org/D57148 llvm-svn: 352518		2019-01-29 16:47:27 +00:00
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AArch64	[llvm-mca] Update tests for Exynos (NFC)	2019-01-11 19:36:27 +00:00
ARM	[llvm-mca] Add support for instructions with a variadic number of operands.	2018-11-25 12:46:24 +00:00
SystemZ	[MCA] Add support for BeginGroup/EndGroup.	2018-12-17 14:27:33 +00:00
X86	[X86][Btver2] Improved latency/throughput model for scalar int-to-float conversions.	2019-01-29 16:47:27 +00:00
invalid_input_file_name.test	Replace unused output filenames with /dev/null in tests	2018-07-02 18:16:44 +00:00
lit.local.cfg	…