127 lines
4.9 KiB
LLVM
127 lines
4.9 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32:
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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define amdgpu_kernel void @store_build_vector_multiple_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0,
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<4 x i32> addrspace(1)* noalias %out1,
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i32 addrspace(1)* noalias %out2,
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i32 addrspace(1)* %in) {
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%elt0 = load volatile i32, i32 addrspace(1)* %in
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%elt1 = load volatile i32, i32 addrspace(1)* %in
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%elt2 = load volatile i32, i32 addrspace(1)* %in
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%elt3 = load volatile i32, i32 addrspace(1)* %in
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%vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
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store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0
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store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out1
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%extract0 = extractelement <4 x i32> %vec3, i32 0
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%extract1 = extractelement <4 x i32> %vec3, i32 1
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%extract2 = extractelement <4 x i32> %vec3, i32 2
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%extract3 = extractelement <4 x i32> %vec3, i32 3
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store volatile i32 %extract0, i32 addrspace(1)* %out2
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store volatile i32 %extract1, i32 addrspace(1)* %out2
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store volatile i32 %extract2, i32 addrspace(1)* %out2
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store volatile i32 %extract3, i32 addrspace(1)* %out2
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ret void
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}
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; GCN-LABEL: {{^}}store_build_vector_multiple_extract_uses_v4i32:
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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; GCN: buffer_store_dword
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define amdgpu_kernel void @store_build_vector_multiple_extract_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0,
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<4 x i32> addrspace(1)* noalias %out1,
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i32 addrspace(1)* noalias %out2,
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i32 addrspace(1)* %in) {
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%elt0 = load volatile i32, i32 addrspace(1)* %in
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%elt1 = load volatile i32, i32 addrspace(1)* %in
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%elt2 = load volatile i32, i32 addrspace(1)* %in
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%elt3 = load volatile i32, i32 addrspace(1)* %in
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%vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
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%extract0 = extractelement <4 x i32> %vec3, i32 0
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%extract1 = extractelement <4 x i32> %vec3, i32 1
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%extract2 = extractelement <4 x i32> %vec3, i32 2
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%extract3 = extractelement <4 x i32> %vec3, i32 3
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%op0 = add i32 %extract0, 3
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%op1 = sub i32 %extract1, 9
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%op2 = xor i32 %extract2, 1231412
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%op3 = and i32 %extract3, 258233412312
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store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0
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store volatile i32 %op0, i32 addrspace(1)* %out2
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store volatile i32 %op1, i32 addrspace(1)* %out2
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store volatile i32 %op2, i32 addrspace(1)* %out2
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store volatile i32 %op3, i32 addrspace(1)* %out2
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ret void
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}
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; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32_bitcast_to_v2i64:
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_load_dword
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; GCN: buffer_store_dwordx4
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; GCN: buffer_store_dwordx2
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @store_build_vector_multiple_uses_v4i32_bitcast_to_v2i64(<2 x i64> addrspace(1)* noalias %out0,
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<4 x i32> addrspace(1)* noalias %out1,
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i64 addrspace(1)* noalias %out2,
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i32 addrspace(1)* %in) {
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%elt0 = load volatile i32, i32 addrspace(1)* %in
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%elt1 = load volatile i32, i32 addrspace(1)* %in
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%elt2 = load volatile i32, i32 addrspace(1)* %in
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%elt3 = load volatile i32, i32 addrspace(1)* %in
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%vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3
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%bc.vec3 = bitcast <4 x i32> %vec3 to <2 x i64>
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store <2 x i64> %bc.vec3, <2 x i64> addrspace(1)* %out0
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%extract0 = extractelement <2 x i64> %bc.vec3, i32 0
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%extract1 = extractelement <2 x i64> %bc.vec3, i32 1
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store volatile i64 %extract0, i64 addrspace(1)* %out2
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store volatile i64 %extract1, i64 addrspace(1)* %out2
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ret void
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}
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