72 lines
3.1 KiB
LLVM
72 lines
3.1 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck --check-prefix=SI --check-prefix=CHECK %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck --check-prefix=CI --check-prefix=CHECK %s
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define amdgpu_kernel void @use_gep_address_space([1024 x i32] addrspace(3)* %array) nounwind {
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; CHECK-LABEL: {{^}}use_gep_address_space:
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; CHECK: v_mov_b32_e32 [[PTR:v[0-9]+]], s{{[0-9]+}}
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; CHECK: ds_write_b32 [[PTR]], v{{[0-9]+}} offset:64
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%p = getelementptr [1024 x i32], [1024 x i32] addrspace(3)* %array, i16 0, i16 16
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store i32 99, i32 addrspace(3)* %p
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ret void
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}
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; CHECK-LABEL: {{^}}use_gep_address_space_large_offset:
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; The LDS offset will be 65536 bytes, which is larger than the size of LDS on
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; SI, which is why it is being OR'd with the base pointer.
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; SI: s_bitset1_b32
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; CI: s_add_i32
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; CHECK: ds_write_b32
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define amdgpu_kernel void @use_gep_address_space_large_offset([1024 x i32] addrspace(3)* %array) nounwind {
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%p = getelementptr [1024 x i32], [1024 x i32] addrspace(3)* %array, i16 0, i16 16384
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store i32 99, i32 addrspace(3)* %p
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ret void
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}
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; CHECK-LABEL: {{^}}gep_as_vector_v4:
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; SI: s_add_i32
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; SI: s_add_i32
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; SI: s_add_i32
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; SI: s_add_i32
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; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
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; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
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; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
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; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
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; CHECK: s_endpgm
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define amdgpu_kernel void @gep_as_vector_v4(<4 x [1024 x i32] addrspace(3)*> %array) nounwind {
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%p = getelementptr [1024 x i32], <4 x [1024 x i32] addrspace(3)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
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%p0 = extractelement <4 x i32 addrspace(3)*> %p, i32 0
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%p1 = extractelement <4 x i32 addrspace(3)*> %p, i32 1
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%p2 = extractelement <4 x i32 addrspace(3)*> %p, i32 2
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%p3 = extractelement <4 x i32 addrspace(3)*> %p, i32 3
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store i32 99, i32 addrspace(3)* %p0
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store i32 99, i32 addrspace(3)* %p1
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store i32 99, i32 addrspace(3)* %p2
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store i32 99, i32 addrspace(3)* %p3
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ret void
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}
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; CHECK-LABEL: {{^}}gep_as_vector_v2:
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; SI: s_add_i32
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; SI: s_add_i32
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; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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; CHECK-DAG: v_mov_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}
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; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
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; CI-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:64
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; CHECK: s_endpgm
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define amdgpu_kernel void @gep_as_vector_v2(<2 x [1024 x i32] addrspace(3)*> %array) nounwind {
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%p = getelementptr [1024 x i32], <2 x [1024 x i32] addrspace(3)*> %array, <2 x i16> zeroinitializer, <2 x i16> <i16 16, i16 16>
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%p0 = extractelement <2 x i32 addrspace(3)*> %p, i32 0
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%p1 = extractelement <2 x i32 addrspace(3)*> %p, i32 1
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store i32 99, i32 addrspace(3)* %p0
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store i32 99, i32 addrspace(3)* %p1
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ret void
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}
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