169 lines
6.8 KiB
LLVM
169 lines
6.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX6 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX8 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
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define amdgpu_kernel void @sin_f16(half addrspace(1)* %r, half addrspace(1)* %a) {
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; GFX6-LABEL: sin_f16:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_mov_b32 s10, s2
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; GFX6-NEXT: s_mov_b32 s11, s3
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_mov_b32 s8, s6
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; GFX6-NEXT: s_mov_b32 s9, s7
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; GFX6-NEXT: buffer_load_ushort v0, off, s[8:11], 0
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; GFX6-NEXT: s_mov_b32 s0, s4
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; GFX6-NEXT: s_mov_b32 s1, s5
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX6-NEXT: v_mul_f32_e32 v0, 0x3e22f983, v0
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; GFX6-NEXT: v_fract_f32_e32 v0, v0
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; GFX6-NEXT: v_sin_f32_e32 v0, v0
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; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX8-LABEL: sin_f16:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
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; GFX8-NEXT: flat_load_ushort v0, v[0:1]
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: v_mul_f16_e32 v0, 0.15915494, v0
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; GFX8-NEXT: v_fract_f16_e32 v0, v0
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; GFX8-NEXT: v_sin_f16_e32 v2, v0
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: flat_store_short v[0:1], v2
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; GFX8-NEXT: s_endpgm
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;
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; GFX9-LABEL: sin_f16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_ushort v1, v0, s[2:3]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mul_f16_e32 v1, 0.15915494, v1
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; GFX9-NEXT: v_sin_f16_e32 v1, v1
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; GFX9-NEXT: global_store_short v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: sin_f16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: global_load_ushort v1, v0, s[2:3]
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_mul_f16_e32 v1, 0.15915494, v1
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; GFX10-NEXT: v_sin_f16_e32 v1, v1
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; GFX10-NEXT: global_store_short v0, v1, s[0:1]
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; GFX10-NEXT: s_endpgm
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%a.val = load half, half addrspace(1)* %a
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%r.val = call half @llvm.sin.f16(half %a.val)
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store half %r.val, half addrspace(1)* %r
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ret void
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}
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define amdgpu_kernel void @sin_v2f16(<2 x half> addrspace(1)* %r, <2 x half> addrspace(1)* %a) {
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; GFX6-LABEL: sin_v2f16:
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; GFX6: ; %bb.0:
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; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_mov_b32 s10, s2
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; GFX6-NEXT: s_mov_b32 s11, s3
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_mov_b32 s8, s6
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; GFX6-NEXT: s_mov_b32 s9, s7
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; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; GFX6-NEXT: s_mov_b32 s0, 0x3e22f983
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; GFX6-NEXT: s_mov_b32 s1, s5
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; GFX6-NEXT: s_waitcnt vmcnt(0)
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; GFX6-NEXT: v_cvt_f32_f16_e32 v1, v0
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; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX6-NEXT: v_cvt_f32_f16_e32 v0, v0
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; GFX6-NEXT: v_mul_f32_e32 v1, s0, v1
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; GFX6-NEXT: v_fract_f32_e32 v1, v1
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; GFX6-NEXT: v_mul_f32_e32 v0, s0, v0
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; GFX6-NEXT: v_fract_f32_e32 v0, v0
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; GFX6-NEXT: v_sin_f32_e32 v0, v0
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; GFX6-NEXT: v_sin_f32_e32 v1, v1
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; GFX6-NEXT: s_mov_b32 s0, s4
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; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX6-NEXT: v_cvt_f16_f32_e32 v1, v1
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; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
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; GFX6-NEXT: v_or_b32_e32 v0, v1, v0
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; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX8-LABEL: sin_v2f16:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
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; GFX8-NEXT: flat_load_dword v0, v[0:1]
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; GFX8-NEXT: v_mov_b32_e32 v1, 0x3118
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; GFX8-NEXT: s_waitcnt vmcnt(0)
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; GFX8-NEXT: v_mul_f16_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; GFX8-NEXT: v_mul_f16_e32 v0, 0.15915494, v0
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; GFX8-NEXT: v_fract_f16_e32 v1, v1
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; GFX8-NEXT: v_fract_f16_e32 v0, v0
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; GFX8-NEXT: v_sin_f16_sdwa v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD
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; GFX8-NEXT: v_sin_f16_e32 v3, v0
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
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; GFX8-NEXT: flat_store_dword v[0:1], v2
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; GFX8-NEXT: s_endpgm
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;
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; GFX9-LABEL: sin_v2f16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: v_mov_b32_e32 v2, 0x3118
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_mul_f16_e32 v3, 0.15915494, v1
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; GFX9-NEXT: v_mul_f16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; GFX9-NEXT: v_sin_f16_e32 v3, v3
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; GFX9-NEXT: v_sin_f16_e32 v1, v1
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; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v3
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; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
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; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: sin_v2f16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: v_mov_b32_e32 v3, 0x3118
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: v_mul_f16_e32 v2, 0.15915494, v1
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; GFX10-NEXT: v_mul_f16_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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; GFX10-NEXT: v_sin_f16_e32 v2, v2
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; GFX10-NEXT: v_sin_f16_e32 v1, v1
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; GFX10-NEXT: v_and_b32_e32 v2, 0xffff, v2
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; GFX10-NEXT: v_lshl_or_b32 v1, v1, 16, v2
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; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
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; GFX10-NEXT: s_endpgm
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%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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%r.val = call <2 x half> @llvm.sin.v2f16(<2 x half> %a.val)
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store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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ret void
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}
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declare half @llvm.sin.f16(half %a)
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declare <2 x half> @llvm.sin.v2f16(<2 x half> %a)
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