259 lines
6.9 KiB
LLVM
259 lines
6.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IF %s
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; For RV64F, fcvt.l.s is semantically equivalent to fcvt.w.s in this case
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; because fptosi will produce poison if the result doesn't fit into an i32.
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define i32 @fcvt_w_s(float %a) nounwind {
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; RV32IF-LABEL: fcvt_w_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_w_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
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; RV64IF-NEXT: ret
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%1 = fptosi float %a to i32
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ret i32 %1
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}
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; For RV64F, fcvt.lu.s is semantically equivalent to fcvt.wu.s in this case
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; because fptoui will produce poison if the result doesn't fit into an i32.
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define i32 @fcvt_wu_s(float %a) nounwind {
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; RV32IF-LABEL: fcvt_wu_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_wu_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
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; RV64IF-NEXT: ret
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%1 = fptoui float %a to i32
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ret i32 %1
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}
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define i32 @fmv_x_w(float %a, float %b) nounwind {
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; RV32IF-LABEL: fmv_x_w:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fmv_x_w:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a1
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; RV64IF-NEXT: fmv.w.x ft1, a0
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; RV64IF-NEXT: fadd.s ft0, ft1, ft0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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; Ensure fmv.x.w is generated even for a soft float calling convention
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%1 = fadd float %a, %b
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%2 = bitcast float %1 to i32
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ret i32 %2
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}
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define float @fcvt_s_w(i32 %a) nounwind {
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; RV32IF-LABEL: fcvt_s_w:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fcvt.s.w ft0, a0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_s_w:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.w ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = sitofp i32 %a to float
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ret float %1
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}
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define float @fcvt_s_wu(i32 %a) nounwind {
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; RV32IF-LABEL: fcvt_s_wu:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fcvt.s.wu ft0, a0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_s_wu:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.wu ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = uitofp i32 %a to float
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ret float %1
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}
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define float @fmv_w_x(i32 %a, i32 %b) nounwind {
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; RV32IF-LABEL: fmv_w_x:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: fadd.s ft0, ft0, ft1
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fmv_w_x:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fmv.w.x ft1, a1
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; RV64IF-NEXT: fadd.s ft0, ft0, ft1
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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; Ensure fmv.w.x is generated even for a soft float calling convention
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%1 = bitcast i32 %a to float
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%2 = bitcast i32 %b to float
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%3 = fadd float %1, %2
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ret float %3
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}
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define i64 @fcvt_l_s(float %a) nounwind {
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; RV32IF-LABEL: fcvt_l_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call __fixsfdi@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_l_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
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; RV64IF-NEXT: ret
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%1 = fptosi float %a to i64
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ret i64 %1
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}
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define i64 @fcvt_lu_s(float %a) nounwind {
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; RV32IF-LABEL: fcvt_lu_s:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call __fixunssfdi@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_lu_s:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fmv.w.x ft0, a0
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; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
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; RV64IF-NEXT: ret
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%1 = fptoui float %a to i64
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ret i64 %1
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}
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define float @fcvt_s_l(i64 %a) nounwind {
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; RV32IF-LABEL: fcvt_s_l:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call __floatdisf@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_s_l:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.l ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = sitofp i64 %a to float
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ret float %1
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}
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define float @fcvt_s_lu(i64 %a) nounwind {
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; RV32IF-LABEL: fcvt_s_lu:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IF-NEXT: call __floatundisf@plt
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; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_s_lu:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.lu ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = uitofp i64 %a to float
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ret float %1
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}
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define float @fcvt_s_w_i8(i8 signext %a) nounwind {
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; RV32IF-LABEL: fcvt_s_w_i8:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fcvt.s.w ft0, a0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_s_w_i8:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.w ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = sitofp i8 %a to float
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ret float %1
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}
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define float @fcvt_s_wu_i8(i8 zeroext %a) nounwind {
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; RV32IF-LABEL: fcvt_s_wu_i8:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fcvt.s.wu ft0, a0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_s_wu_i8:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.wu ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = uitofp i8 %a to float
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ret float %1
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}
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define float @fcvt_s_w_i16(i16 signext %a) nounwind {
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; RV32IF-LABEL: fcvt_s_w_i16:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fcvt.s.w ft0, a0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_s_w_i16:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.w ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = sitofp i16 %a to float
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ret float %1
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}
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define float @fcvt_s_wu_i16(i16 zeroext %a) nounwind {
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; RV32IF-LABEL: fcvt_s_wu_i16:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fcvt.s.wu ft0, a0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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;
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; RV64IF-LABEL: fcvt_s_wu_i16:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: fcvt.s.wu ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%1 = uitofp i16 %a to float
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ret float %1
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}
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