453 lines
13 KiB
LLVM
453 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi ilp32f < %s \
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; RUN: | FileCheck -check-prefix=RV32IZFH %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh -verify-machineinstrs \
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; RUN: -target-abi lp64f < %s \
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; RUN: | FileCheck -check-prefix=RV64IZFH %s
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; These tests are each targeted at a particular RISC-V FPU instruction. Most
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; other files in this folder exercise LLVM IR instructions that don't directly
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; match a RISC-V instruction.
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define half @fadd_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fadd_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fadd.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fadd_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, %b
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ret half %1
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}
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define half @fsub_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fsub_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fsub.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fsub_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fsub.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fsub half %a, %b
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ret half %1
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}
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define half @fmul_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fmul_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmul.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmul_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmul.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fmul half %a, %b
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ret half %1
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}
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define half @fdiv_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fdiv_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fdiv.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fdiv_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fdiv.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fdiv half %a, %b
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ret half %1
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}
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declare half @llvm.sqrt.f16(half)
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define half @fsqrt_s(half %a) nounwind {
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; RV32IZFH-LABEL: fsqrt_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fsqrt.h fa0, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fsqrt_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fsqrt.h fa0, fa0
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.sqrt.f16(half %a)
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ret half %1
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}
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declare half @llvm.copysign.f16(half, half)
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define half @fsgnj_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fsgnj_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fsgnj.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fsgnj_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fsgnj.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.copysign.f16(half %a, half %b)
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ret half %1
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}
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; This function performs extra work to ensure that
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; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
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define i32 @fneg_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fneg_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fadd.h ft0, fa0, fa0
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; RV32IZFH-NEXT: fneg.h ft1, ft0
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; RV32IZFH-NEXT: feq.h a0, ft0, ft1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fneg_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h ft0, fa0, fa0
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; RV64IZFH-NEXT: fneg.h ft1, ft0
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; RV64IZFH-NEXT: feq.h a0, ft0, ft1
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, %a
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%2 = fneg half %1
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%3 = fcmp oeq half %1, %2
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%4 = zext i1 %3 to i32
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ret i32 %4
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}
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; This function performs extra work to ensure that
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; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
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define half @fsgnjn_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fsgnjn_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV32IZFH-NEXT: fsgnjn.h fa0, fa0, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fsgnjn_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV64IZFH-NEXT: fsgnjn.h fa0, fa0, ft0
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, %b
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%2 = fneg half %1
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%3 = call half @llvm.copysign.f16(half %a, half %2)
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ret half %3
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}
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declare half @llvm.fabs.f16(half)
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; This function performs extra work to ensure that
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; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
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define half @fabs_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fabs_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV32IZFH-NEXT: fabs.h ft1, ft0
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; RV32IZFH-NEXT: fadd.h fa0, ft1, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fabs_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fadd.h ft0, fa0, fa1
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; RV64IZFH-NEXT: fabs.h ft1, ft0
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; RV64IZFH-NEXT: fadd.h fa0, ft1, ft0
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; RV64IZFH-NEXT: ret
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%1 = fadd half %a, %b
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%2 = call half @llvm.fabs.f16(half %1)
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%3 = fadd half %2, %1
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ret half %3
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}
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declare half @llvm.minnum.f16(half, half)
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define half @fmin_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fmin_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmin.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmin_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmin.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.minnum.f16(half %a, half %b)
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ret half %1
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}
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declare half @llvm.maxnum.f16(half, half)
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define half @fmax_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fmax_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmax.h fa0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmax_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmax.h fa0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.maxnum.f16(half %a, half %b)
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ret half %1
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}
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define i32 @feq_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: feq_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: feq.h a0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: feq_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: feq.h a0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fcmp oeq half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @flt_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: flt_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: flt.h a0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: flt_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: flt.h a0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fcmp olt half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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define i32 @fle_s(half %a, half %b) nounwind {
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; RV32IZFH-LABEL: fle_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fle.h a0, fa0, fa1
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fle_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fle.h a0, fa0, fa1
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; RV64IZFH-NEXT: ret
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%1 = fcmp ole half %a, %b
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%2 = zext i1 %1 to i32
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ret i32 %2
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}
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declare half @llvm.fma.f16(half, half, half)
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define half @fmadd_s(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fmadd_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmadd_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.fma.f16(half %a, half %b, half %c)
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ret half %1
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}
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define half @fmsub_s(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fmsub_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmsub_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
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; RV64IZFH-NEXT: ret
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%c_ = fadd half 0.0, %c ; avoid negation using xor
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%negc = fsub half -0.0, %c_
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%1 = call half @llvm.fma.f16(half %a, half %b, half %negc)
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ret half %1
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}
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define half @fnmadd_s(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmadd_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
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; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmadd_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
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; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa1, ft0
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; RV64IZFH-NEXT: ret
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%a_ = fadd half 0.0, %a
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%c_ = fadd half 0.0, %c
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%nega = fsub half -0.0, %a_
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%negc = fsub half -0.0, %c_
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%1 = call half @llvm.fma.f16(half %nega, half %b, half %negc)
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ret half %1
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}
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define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmadd_s_2:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft1, fa1, ft0
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; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV32IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmadd_s_2:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft1, fa1, ft0
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; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV64IZFH-NEXT: fnmadd.h fa0, ft1, fa0, ft0
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; RV64IZFH-NEXT: ret
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%b_ = fadd half 0.0, %b
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%c_ = fadd half 0.0, %c
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%negb = fsub half -0.0, %b_
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%negc = fsub half -0.0, %c_
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%1 = call half @llvm.fma.f16(half %a, half %negb, half %negc)
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ret half %1
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}
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define half @fnmsub_s(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmsub_s:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0
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; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmsub_s:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft0, fa0, ft0
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; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
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; RV64IZFH-NEXT: ret
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%a_ = fadd half 0.0, %a
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%nega = fsub half -0.0, %a_
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%1 = call half @llvm.fma.f16(half %nega, half %b, half %c)
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ret half %1
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}
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define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmsub_s_2:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
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; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fnmsub_s_2:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
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; RV64IZFH-NEXT: fnmsub.h fa0, ft0, fa0, fa2
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; RV64IZFH-NEXT: ret
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%b_ = fadd half 0.0, %b
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%negb = fsub half -0.0, %b_
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%1 = call half @llvm.fma.f16(half %a, half %negb, half %c)
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ret half %1
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}
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define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fmadd_s_contract:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmadd_s_contract:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
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; RV64IZFH-NEXT: ret
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%1 = fmul contract half %a, %b
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%2 = fadd contract half %1, %c
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ret half %2
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}
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define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fmsub_s_contract:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fmv.h.x ft0, zero
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; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV32IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: fmsub_s_contract:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fmv.h.x ft0, zero
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; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
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; RV64IZFH-NEXT: fmsub.h fa0, fa0, fa1, ft0
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; RV64IZFH-NEXT: ret
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%c_ = fadd half 0.0, %c ; avoid negation using xor
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%1 = fmul contract half %a, %b
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%2 = fsub contract half %1, %c_
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ret half %2
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}
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define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
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; RV32IZFH-LABEL: fnmadd_s_contract:
|
|
; RV32IZFH: # %bb.0:
|
|
; RV32IZFH-NEXT: fmv.h.x ft0, zero
|
|
; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
|
|
; RV32IZFH-NEXT: fadd.h ft2, fa1, ft0
|
|
; RV32IZFH-NEXT: fadd.h ft0, fa2, ft0
|
|
; RV32IZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
|
|
; RV32IZFH-NEXT: ret
|
|
;
|
|
; RV64IZFH-LABEL: fnmadd_s_contract:
|
|
; RV64IZFH: # %bb.0:
|
|
; RV64IZFH-NEXT: fmv.h.x ft0, zero
|
|
; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
|
|
; RV64IZFH-NEXT: fadd.h ft2, fa1, ft0
|
|
; RV64IZFH-NEXT: fadd.h ft0, fa2, ft0
|
|
; RV64IZFH-NEXT: fnmadd.h fa0, ft1, ft2, ft0
|
|
; RV64IZFH-NEXT: ret
|
|
%a_ = fadd half 0.0, %a ; avoid negation using xor
|
|
%b_ = fadd half 0.0, %b ; avoid negation using xor
|
|
%c_ = fadd half 0.0, %c ; avoid negation using xor
|
|
%1 = fmul contract half %a_, %b_
|
|
%2 = fneg half %1
|
|
%3 = fsub contract half %2, %c_
|
|
ret half %3
|
|
}
|
|
|
|
define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
|
|
; RV32IZFH-LABEL: fnmsub_s_contract:
|
|
; RV32IZFH: # %bb.0:
|
|
; RV32IZFH-NEXT: fmv.h.x ft0, zero
|
|
; RV32IZFH-NEXT: fadd.h ft1, fa0, ft0
|
|
; RV32IZFH-NEXT: fadd.h ft0, fa1, ft0
|
|
; RV32IZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
|
|
; RV32IZFH-NEXT: ret
|
|
;
|
|
; RV64IZFH-LABEL: fnmsub_s_contract:
|
|
; RV64IZFH: # %bb.0:
|
|
; RV64IZFH-NEXT: fmv.h.x ft0, zero
|
|
; RV64IZFH-NEXT: fadd.h ft1, fa0, ft0
|
|
; RV64IZFH-NEXT: fadd.h ft0, fa1, ft0
|
|
; RV64IZFH-NEXT: fnmsub.h fa0, ft1, ft0, fa2
|
|
; RV64IZFH-NEXT: ret
|
|
%a_ = fadd half 0.0, %a ; avoid negation using xor
|
|
%b_ = fadd half 0.0, %b ; avoid negation using xor
|
|
%1 = fmul contract half %a_, %b_
|
|
%2 = fsub contract half %c, %1
|
|
ret half %2
|
|
}
|