162 lines
5.0 KiB
LLVM
162 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbt -disable-block-placement -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IBT %s
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define i32 @foo(i32 %a, i32 *%b) nounwind {
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; RV32I-LABEL: foo:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: beq a0, a2, .LBB0_2
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; RV32I-NEXT: # %bb.1:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_2:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: bne a0, a2, .LBB0_4
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; RV32I-NEXT: # %bb.3:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_4:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: bltu a2, a0, .LBB0_6
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; RV32I-NEXT: # %bb.5:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_6:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: bgeu a0, a2, .LBB0_8
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; RV32I-NEXT: # %bb.7:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_8:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: bltu a0, a2, .LBB0_10
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; RV32I-NEXT: # %bb.9:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_10:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: bgeu a2, a0, .LBB0_12
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; RV32I-NEXT: # %bb.11:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_12:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: blt a2, a0, .LBB0_14
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; RV32I-NEXT: # %bb.13:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_14:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: bge a0, a2, .LBB0_16
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; RV32I-NEXT: # %bb.15:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_16:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: blt a0, a2, .LBB0_18
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; RV32I-NEXT: # %bb.17:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_18:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: bge a2, a0, .LBB0_20
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; RV32I-NEXT: # %bb.19:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_20:
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; RV32I-NEXT: lw a2, 0(a1)
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; RV32I-NEXT: blez a2, .LBB0_22
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; RV32I-NEXT: # %bb.21:
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; RV32I-NEXT: mv a0, a2
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; RV32I-NEXT: .LBB0_22:
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; RV32I-NEXT: lw a1, 0(a1)
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; RV32I-NEXT: bgez a2, .LBB0_24
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; RV32I-NEXT: # %bb.23:
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: .LBB0_24:
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; RV32I-NEXT: ret
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;
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; RV32IBT-LABEL: foo:
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; RV32IBT: # %bb.0:
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; RV32IBT-NEXT: lw a2, 0(a1)
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; RV32IBT-NEXT: lw a3, 0(a1)
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; RV32IBT-NEXT: xor a4, a0, a2
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; RV32IBT-NEXT: cmov a0, a4, a2, a0
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; RV32IBT-NEXT: lw a2, 0(a1)
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; RV32IBT-NEXT: xor a4, a0, a3
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; RV32IBT-NEXT: cmov a0, a4, a0, a3
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; RV32IBT-NEXT: lw a3, 0(a1)
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; RV32IBT-NEXT: sltu a4, a2, a0
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; RV32IBT-NEXT: cmov a0, a4, a0, a2
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; RV32IBT-NEXT: lw a2, 0(a1)
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; RV32IBT-NEXT: sltu a4, a0, a3
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; RV32IBT-NEXT: cmov a0, a4, a3, a0
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; RV32IBT-NEXT: lw a3, 0(a1)
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; RV32IBT-NEXT: sltu a4, a0, a2
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; RV32IBT-NEXT: cmov a0, a4, a0, a2
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; RV32IBT-NEXT: lw a2, 0(a1)
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; RV32IBT-NEXT: sltu a4, a3, a0
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; RV32IBT-NEXT: cmov a0, a4, a3, a0
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; RV32IBT-NEXT: lw a3, 0(a1)
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; RV32IBT-NEXT: slt a4, a2, a0
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; RV32IBT-NEXT: cmov a0, a4, a0, a2
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; RV32IBT-NEXT: lw a2, 0(a1)
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; RV32IBT-NEXT: slt a4, a0, a3
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; RV32IBT-NEXT: cmov a0, a4, a3, a0
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; RV32IBT-NEXT: lw a3, 0(a1)
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; RV32IBT-NEXT: slt a4, a0, a2
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; RV32IBT-NEXT: lw a5, 0(a1)
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; RV32IBT-NEXT: cmov a0, a4, a0, a2
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; RV32IBT-NEXT: slt a2, a3, a0
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; RV32IBT-NEXT: cmov a0, a2, a3, a0
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; RV32IBT-NEXT: slti a2, a5, 1
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; RV32IBT-NEXT: lw a1, 0(a1)
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; RV32IBT-NEXT: cmov a0, a2, a0, a5
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; RV32IBT-NEXT: addi a2, zero, -1
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; RV32IBT-NEXT: slt a2, a2, a5
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; RV32IBT-NEXT: cmov a0, a2, a0, a1
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; RV32IBT-NEXT: ret
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%val1 = load volatile i32, i32* %b
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%tst1 = icmp eq i32 %a, %val1
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%val2 = select i1 %tst1, i32 %a, i32 %val1
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%val3 = load volatile i32, i32* %b
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%tst2 = icmp ne i32 %val2, %val3
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%val4 = select i1 %tst2, i32 %val2, i32 %val3
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%val5 = load volatile i32, i32* %b
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%tst3 = icmp ugt i32 %val4, %val5
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%val6 = select i1 %tst3, i32 %val4, i32 %val5
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%val7 = load volatile i32, i32* %b
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%tst4 = icmp uge i32 %val6, %val7
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%val8 = select i1 %tst4, i32 %val6, i32 %val7
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%val9 = load volatile i32, i32* %b
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%tst5 = icmp ult i32 %val8, %val9
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%val10 = select i1 %tst5, i32 %val8, i32 %val9
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%val11 = load volatile i32, i32* %b
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%tst6 = icmp ule i32 %val10, %val11
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%val12 = select i1 %tst6, i32 %val10, i32 %val11
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%val13 = load volatile i32, i32* %b
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%tst7 = icmp sgt i32 %val12, %val13
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%val14 = select i1 %tst7, i32 %val12, i32 %val13
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%val15 = load volatile i32, i32* %b
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%tst8 = icmp sge i32 %val14, %val15
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%val16 = select i1 %tst8, i32 %val14, i32 %val15
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%val17 = load volatile i32, i32* %b
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%tst9 = icmp slt i32 %val16, %val17
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%val18 = select i1 %tst9, i32 %val16, i32 %val17
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%val19 = load volatile i32, i32* %b
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%tst10 = icmp sle i32 %val18, %val19
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%val20 = select i1 %tst10, i32 %val18, i32 %val19
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%val21 = load volatile i32, i32* %b
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%tst11 = icmp slt i32 %val21, 1
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%val22 = select i1 %tst11, i32 %val20, i32 %val21
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%val23 = load volatile i32, i32* %b
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%tst12 = icmp sgt i32 %val21, -1
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%val24 = select i1 %tst12, i32 %val22, i32 %val23
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ret i32 %val24
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}
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