454 lines
17 KiB
C++
454 lines
17 KiB
C++
//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MipsISELLOWERING_H
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#define MipsISELLOWERING_H
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#include "Mips.h"
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Target/TargetLowering.h"
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#include <deque>
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#include <string>
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namespace llvm {
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namespace MipsISD {
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enum NodeType {
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// Start the numbering from where ISD NodeType finishes.
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// Jump and link (call)
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JmpLink,
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// Tail call
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TailCall,
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// Get the Higher 16 bits from a 32-bit immediate
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// No relation with Mips Hi register
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Hi,
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// Get the Lower 16 bits from a 32-bit immediate
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// No relation with Mips Lo register
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Lo,
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// Handle gp_rel (small data/bss sections) relocation.
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GPRel,
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// Thread Pointer
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ThreadPointer,
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// Floating Point Branch Conditional
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FPBrcond,
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// Floating Point Compare
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FPCmp,
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// Floating Point Conditional Moves
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CMovFP_T,
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CMovFP_F,
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// Floating Point Rounding
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FPRound,
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// Return
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Ret,
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EH_RETURN,
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// MAdd/Sub nodes
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MAdd,
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MAddu,
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MSub,
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MSubu,
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// DivRem(u)
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DivRem,
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DivRemU,
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BuildPairF64,
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ExtractElementF64,
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Wrapper,
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DynAlloc,
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Sync,
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Ext,
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Ins,
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// EXTR.W instrinsic nodes.
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EXTP,
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EXTPDP,
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EXTR_S_H,
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EXTR_W,
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EXTR_R_W,
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EXTR_RS_W,
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SHILO,
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MTHLIP,
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// DPA.W intrinsic nodes.
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MULSAQ_S_W_PH,
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MAQ_S_W_PHL,
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MAQ_S_W_PHR,
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MAQ_SA_W_PHL,
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MAQ_SA_W_PHR,
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DPAU_H_QBL,
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DPAU_H_QBR,
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DPSU_H_QBL,
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DPSU_H_QBR,
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DPAQ_S_W_PH,
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DPSQ_S_W_PH,
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DPAQ_SA_L_W,
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DPSQ_SA_L_W,
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DPA_W_PH,
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DPS_W_PH,
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DPAQX_S_W_PH,
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DPAQX_SA_W_PH,
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DPAX_W_PH,
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DPSX_W_PH,
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DPSQX_S_W_PH,
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DPSQX_SA_W_PH,
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MULSA_W_PH,
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MULT,
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MULTU,
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MADD_DSP,
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MADDU_DSP,
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MSUB_DSP,
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MSUBU_DSP,
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// Load/Store Left/Right nodes.
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LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LWR,
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SWL,
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SWR,
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LDL,
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LDR,
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SDL,
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SDR
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};
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}
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//===--------------------------------------------------------------------===//
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// TargetLowering Implementation
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//===--------------------------------------------------------------------===//
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class MipsFunctionInfo;
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class MipsTargetLowering : public TargetLowering {
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public:
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explicit MipsTargetLowering(MipsTargetMachine &TM);
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static const MipsTargetLowering *create(MipsTargetMachine &TM);
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virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
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virtual void LowerOperationWrapper(SDNode *N,
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SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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/// ReplaceNodeResults - Replace the results of node with an illegal result
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/// type with new values built out of custom code.
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///
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virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) const;
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/// getTargetNodeName - This method returns the name of a target specific
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// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// getSetCCResultType - get the ISD::SETCC result ValueType
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EVT getSetCCResultType(EVT VT) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
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struct LTStr {
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bool operator()(const char *S1, const char *S2) const {
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return strcmp(S1, S2) < 0;
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}
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};
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protected:
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SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
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SDValue getAddrLocal(SDValue Op, SelectionDAG &DAG, bool HasMips64) const;
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SDValue getAddrGlobal(SDValue Op, SelectionDAG &DAG, unsigned Flag) const;
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SDValue getAddrGlobalLargeGOT(SDValue Op, SelectionDAG &DAG,
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unsigned HiFlag, unsigned LoFlag) const;
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/// This function fills Ops, which is the list of operands that will later
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/// be used when a function call node is created. It also generates
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/// copyToReg nodes to set up argument registers.
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virtual void
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getOpndList(SmallVectorImpl<SDValue> &Ops,
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std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const;
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/// ByValArgInfo - Byval argument information.
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struct ByValArgInfo {
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unsigned FirstIdx; // Index of the first register used.
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unsigned NumRegs; // Number of registers used for this argument.
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unsigned Address; // Offset of the stack area used to pass this argument.
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ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {}
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};
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/// MipsCC - This class provides methods used to analyze formal and call
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/// arguments and inquire about calling convention information.
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class MipsCC {
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public:
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MipsCC(CallingConv::ID CallConv, bool IsO32, CCState &Info);
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void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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bool IsVarArg, bool IsSoftFloat,
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const SDNode *CallNode,
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std::vector<ArgListEntry> &FuncArgs);
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void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
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bool IsSoftFloat,
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Function::const_arg_iterator FuncArg);
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void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
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bool IsSoftFloat, const SDNode *CallNode,
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const Type *RetTy) const;
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void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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bool IsSoftFloat, const Type *RetTy) const;
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const CCState &getCCInfo() const { return CCInfo; }
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/// hasByValArg - Returns true if function has byval arguments.
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bool hasByValArg() const { return !ByValArgs.empty(); }
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/// regSize - Size (in number of bits) of integer registers.
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unsigned regSize() const { return IsO32 ? 4 : 8; }
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/// numIntArgRegs - Number of integer registers available for calls.
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unsigned numIntArgRegs() const;
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/// reservedArgArea - The size of the area the caller reserves for
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/// register arguments. This is 16-byte if ABI is O32.
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unsigned reservedArgArea() const;
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/// Return pointer to array of integer argument registers.
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const uint16_t *intArgRegs() const;
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typedef SmallVector<ByValArgInfo, 2>::const_iterator byval_iterator;
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byval_iterator byval_begin() const { return ByValArgs.begin(); }
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byval_iterator byval_end() const { return ByValArgs.end(); }
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private:
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void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags);
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/// useRegsForByval - Returns true if the calling convention allows the
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/// use of registers to pass byval arguments.
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bool useRegsForByval() const { return CallConv != CallingConv::Fast; }
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/// Return the function that analyzes fixed argument list functions.
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llvm::CCAssignFn *fixedArgFn() const;
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/// Return the function that analyzes variable argument list functions.
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llvm::CCAssignFn *varArgFn() const;
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const uint16_t *shadowRegs() const;
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void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
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unsigned Align);
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/// Return the type of the register which is used to pass an argument or
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/// return a value. This function returns f64 if the argument is an i64
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/// value which has been generated as a result of softening an f128 value.
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/// Otherwise, it just returns VT.
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MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode,
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bool IsSoftFloat) const;
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template<typename Ty>
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void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat,
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const SDNode *CallNode, const Type *RetTy) const;
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CCState &CCInfo;
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CallingConv::ID CallConv;
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bool IsO32;
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SmallVector<ByValArgInfo, 2> ByValArgs;
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};
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// Subtarget Info
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const MipsSubtarget *Subtarget;
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bool HasMips64, IsN64, IsO32;
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private:
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// Lower Operand helpers
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals,
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const SDNode *CallNode, const Type *RetTy) const;
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// Lower Operand specifics
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SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
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SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
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SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
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SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
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bool IsSRA) const;
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SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerADD(SDValue Op, SelectionDAG &DAG) const;
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/// isEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization.
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virtual bool
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isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo,
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unsigned NextStackOffset,
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const MipsFunctionInfo& FI) const = 0;
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/// copyByValArg - Copy argument registers which were used to pass a byval
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/// argument to the stack. Create a stack frame object for the byval
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/// argument.
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void copyByValRegs(SDValue Chain, DebugLoc DL,
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std::vector<SDValue> &OutChains, SelectionDAG &DAG,
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const ISD::ArgFlagsTy &Flags,
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SmallVectorImpl<SDValue> &InVals,
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const Argument *FuncArg,
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const MipsCC &CC, const ByValArgInfo &ByVal) const;
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/// passByValArg - Pass a byval argument in registers or on stack.
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void passByValArg(SDValue Chain, DebugLoc DL,
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std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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SmallVector<SDValue, 8> &MemOpChains, SDValue StackPtr,
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MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg,
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const MipsCC &CC, const ByValArgInfo &ByVal,
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const ISD::ArgFlagsTy &Flags, bool isLittle) const;
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/// writeVarArgRegs - Write variable function arguments passed in registers
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/// to the stack. Also create a stack frame object for the first variable
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/// argument.
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void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC,
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SDValue Chain, DebugLoc DL, SelectionDAG &DAG) const;
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const;
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SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
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SDValue Arg, DebugLoc DL, bool IsTailCall,
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SelectionDAG &DAG) const;
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virtual SDValue
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LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const;
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virtual bool
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CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const;
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virtual SDValue
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LowerReturn(SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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DebugLoc dl, SelectionDAG &DAG) const;
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// Inline asm support
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ConstraintType getConstraintType(const std::string &Constraint) const;
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/// Examine constraint string and operand type and determine a weight value.
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/// The operand object must already have been set up with the operand type.
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ConstraintWeight getSingleConstraintMatchWeight(
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AsmOperandInfo &info, const char *constraint) const;
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std::pair<unsigned, const TargetRegisterClass*>
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getRegForInlineAsmConstraint(const std::string &Constraint,
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EVT VT) const;
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/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
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/// vector. If it is invalid, don't add anything to Ops. If hasMemory is
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/// true it means one of the asm constraint of the inline asm instruction
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/// being processed is 'm'.
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virtual void LowerAsmOperandForConstraint(SDValue Op,
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std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const;
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virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
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virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
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virtual EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
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unsigned SrcAlign,
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bool IsMemset, bool ZeroMemset,
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bool MemcpyStrSrc,
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MachineFunction &MF) const;
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/// isFPImmLegal - Returns true if the target can instruction select the
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/// specified FP immediate natively. If false, the legalizer will
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/// materialize the FP immediate as a load from a constant pool.
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virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
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virtual unsigned getJumpTableEncoding() const;
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MachineBasicBlock *emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Size, unsigned BinOpcode, bool Nand = false) const;
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MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
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bool Nand = false) const;
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MachineBasicBlock *emitAtomicCmpSwap(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size) const;
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MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr *MI,
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MachineBasicBlock *BB, unsigned Size) const;
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};
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/// Create MipsTargetLowering objects.
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const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM);
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const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM);
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}
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#endif // MipsISELLOWERING_H
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