98 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			C++
		
	
	
	
			
		
		
	
	
			98 lines
		
	
	
		
			2.5 KiB
		
	
	
	
		
			C++
		
	
	
	
//===-- R600Defines.h - R600 Helper Macros ----------------------*- C++ -*-===//
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//
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//                     The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef R600DEFINES_H_
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#define R600DEFINES_H_
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#include "llvm/MC/MCRegisterInfo.h"
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// Operand Flags
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#define MO_FLAG_CLAMP (1 << 0)
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#define MO_FLAG_NEG   (1 << 1)
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#define MO_FLAG_ABS   (1 << 2)
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#define MO_FLAG_MASK  (1 << 3)
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#define MO_FLAG_PUSH  (1 << 4)
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#define MO_FLAG_NOT_LAST  (1 << 5)
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#define MO_FLAG_LAST  (1 << 6)
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#define NUM_MO_FLAGS 7
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/// \brief Helper for getting the operand index for the instruction flags
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/// operand.
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#define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3)
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namespace R600_InstFlag {
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  enum TIF {
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    TRANS_ONLY = (1 << 0),
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    TEX = (1 << 1),
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    REDUCTION = (1 << 2),
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    FC = (1 << 3),
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    TRIG = (1 << 4),
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    OP3 = (1 << 5),
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    VECTOR = (1 << 6),
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    //FlagOperand bits 7, 8
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    NATIVE_OPERANDS = (1 << 9),
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    OP1 = (1 << 10),
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    OP2 = (1 << 11)
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  };
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}
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#define HAS_NATIVE_OPERANDS(Flags) ((Flags) & R600_InstFlag::NATIVE_OPERANDS)
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/// \brief Defines for extracting register infomation from register encoding
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#define HW_REG_MASK 0x1ff
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#define HW_CHAN_SHIFT 9
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#define GET_REG_CHAN(reg) ((reg) >> HW_CHAN_SHIFT)
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#define GET_REG_INDEX(reg) ((reg) & HW_REG_MASK)
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namespace R600Operands {
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  enum Ops {
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    DST,
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    UPDATE_EXEC_MASK,
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    UPDATE_PREDICATE,
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    WRITE,
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    OMOD,
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    DST_REL,
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    CLAMP,
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    SRC0,
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    SRC0_NEG,
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    SRC0_REL,
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    SRC0_ABS,
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    SRC0_SEL,
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    SRC1,
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    SRC1_NEG,
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    SRC1_REL,
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    SRC1_ABS,
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    SRC1_SEL,
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    SRC2,
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    SRC2_NEG,
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    SRC2_REL,
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    SRC2_SEL,
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    LAST,
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    PRED_SEL,
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    IMM,
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    COUNT
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 };
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  const static int ALUOpTable[3][R600Operands::COUNT] = {
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//            W        C     S  S  S  S     S  S  S  S     S  S  S
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//            R  O  D  L  S  R  R  R  R  S  R  R  R  R  S  R  R  R  L  P
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//   D  U     I  M  R  A  R  C  C  C  C  R  C  C  C  C  R  C  C  C  A  R  I
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//   S  E  U  T  O  E  M  C  0  0  0  0  C  1  1  1  1  C  2  2  2  S  E  M
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//   T  M  P  E  D  L  P  0  N  R  A  S  1  N  R  A  S  2  N  R  S  T  D  M
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    {0,-1,-1, 1, 2, 3, 4, 5, 6, 7, 8, 9,-1,-1,-1,-1,-1,-1,-1,-1,-1,10,11,12},
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    {0, 1, 2, 3, 4 ,5 ,6 ,7, 8, 9,10,11,12,13,14,15,16,-1,-1,-1,-1,17,18,19},
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    {0,-1,-1,-1,-1, 1, 2, 3, 4, 5,-1, 6, 7, 8, 9,-1,10,11,12,13,14,15,16,17}
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  };
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}
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#endif // R600DEFINES_H_
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