123 lines
4.0 KiB
C++
123 lines
4.0 KiB
C++
//===-- RISCVELFObjectWriter.cpp - RISCV ELF Writer -----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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namespace {
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class RISCVELFObjectWriter : public MCELFObjectTargetWriter {
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public:
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RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit);
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~RISCVELFObjectWriter() override;
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// Return true if the given relocation must be with a symbol rather than
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// section plus offset.
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bool needsRelocateWithSymbol(const MCSymbol &Sym,
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unsigned Type) const override {
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// TODO: this is very conservative, update once RISC-V psABI requirements
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// are clarified.
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return true;
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}
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protected:
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unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
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const MCFixup &Fixup, bool IsPCRel) const override;
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};
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}
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RISCVELFObjectWriter::RISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit)
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: MCELFObjectTargetWriter(Is64Bit, OSABI, ELF::EM_RISCV,
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/*HasRelocationAddend*/ true) {}
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RISCVELFObjectWriter::~RISCVELFObjectWriter() {}
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unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
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const MCValue &Target,
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const MCFixup &Fixup,
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bool IsPCRel) const {
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// Determine the type of the relocation
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switch ((unsigned)Fixup.getKind()) {
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default:
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llvm_unreachable("invalid fixup kind!");
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case FK_Data_4:
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return ELF::R_RISCV_32;
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case FK_Data_8:
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return ELF::R_RISCV_64;
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case FK_Data_Add_1:
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return ELF::R_RISCV_ADD8;
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case FK_Data_Add_2:
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return ELF::R_RISCV_ADD16;
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case FK_Data_Add_4:
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return ELF::R_RISCV_ADD32;
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case FK_Data_Add_8:
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return ELF::R_RISCV_ADD64;
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case FK_Data_Sub_1:
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return ELF::R_RISCV_SUB8;
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case FK_Data_Sub_2:
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return ELF::R_RISCV_SUB16;
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case FK_Data_Sub_4:
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return ELF::R_RISCV_SUB32;
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case FK_Data_Sub_8:
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return ELF::R_RISCV_SUB64;
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case RISCV::fixup_riscv_hi20:
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return ELF::R_RISCV_HI20;
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case RISCV::fixup_riscv_lo12_i:
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return ELF::R_RISCV_LO12_I;
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case RISCV::fixup_riscv_lo12_s:
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return ELF::R_RISCV_LO12_S;
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case RISCV::fixup_riscv_pcrel_hi20:
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return ELF::R_RISCV_PCREL_HI20;
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case RISCV::fixup_riscv_pcrel_lo12_i:
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return ELF::R_RISCV_PCREL_LO12_I;
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case RISCV::fixup_riscv_pcrel_lo12_s:
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return ELF::R_RISCV_PCREL_LO12_S;
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case RISCV::fixup_riscv_got_hi20:
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return ELF::R_RISCV_GOT_HI20;
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case RISCV::fixup_riscv_tprel_hi20:
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return ELF::R_RISCV_TPREL_HI20;
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case RISCV::fixup_riscv_tprel_lo12_i:
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return ELF::R_RISCV_TPREL_LO12_I;
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case RISCV::fixup_riscv_tprel_lo12_s:
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return ELF::R_RISCV_TPREL_LO12_S;
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case RISCV::fixup_riscv_tprel_add:
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return ELF::R_RISCV_TPREL_ADD;
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case RISCV::fixup_riscv_tls_got_hi20:
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return ELF::R_RISCV_TLS_GOT_HI20;
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case RISCV::fixup_riscv_tls_gd_hi20:
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return ELF::R_RISCV_TLS_GD_HI20;
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case RISCV::fixup_riscv_jal:
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return ELF::R_RISCV_JAL;
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case RISCV::fixup_riscv_branch:
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return ELF::R_RISCV_BRANCH;
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case RISCV::fixup_riscv_rvc_jump:
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return ELF::R_RISCV_RVC_JUMP;
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case RISCV::fixup_riscv_rvc_branch:
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return ELF::R_RISCV_RVC_BRANCH;
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case RISCV::fixup_riscv_call:
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return ELF::R_RISCV_CALL;
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case RISCV::fixup_riscv_call_plt:
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return ELF::R_RISCV_CALL_PLT;
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case RISCV::fixup_riscv_relax:
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return ELF::R_RISCV_RELAX;
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case RISCV::fixup_riscv_align:
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return ELF::R_RISCV_ALIGN;
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}
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}
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std::unique_ptr<MCObjectTargetWriter>
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llvm::createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) {
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return llvm::make_unique<RISCVELFObjectWriter>(OSABI, Is64Bit);
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}
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