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llvm-project/llvm/test/CodeGen/RISCV/VentusGPGPU/float.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mcpu=ventus-gpgpu -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=VENTUS %s
define float @fadd_v(float noundef %a, float noundef %b) {
; VENTUS-LABEL: fadd_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfadd.vv v0, v0, v1
; VENTUS-NEXT: ret
entry:
%add = fadd float %a, %b
ret float %add
}
define float @fadd_f(float noundef %a) {
; VENTUS-LABEL: fadd_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(global_val)
; VENTUS-NEXT: lw a0, %lo(global_val)(a0)
; VENTUS-NEXT: vfadd.vf v0, v0, a0
; VENTUS-NEXT: ret
entry:
%val = load float, ptr @global_val, align 4
%add = fadd float %a, %val
ret float %add
}
define float @fsub_v(float noundef %a, float noundef %b) {
; VENTUS-LABEL: fsub_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfsub.vv v0, v0, v1
; VENTUS-NEXT: ret
entry:
%add = fsub float %a, %b
ret float %add
}
define float @fsub_f(float noundef %a) {
; VENTUS-LABEL: fsub_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(global_val)
; VENTUS-NEXT: lw a0, %lo(global_val)(a0)
; VENTUS-NEXT: vfsub.vf v0, v0, a0
; VENTUS-NEXT: ret
entry:
%val = load float, ptr @global_val, align 4
%add = fsub float %a, %val
ret float %add
}
define float @fmul_v(float noundef %a, float noundef %b) {
; VENTUS-LABEL: fmul_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmul.vv v0, v0, v1
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, %b
ret float %mul
}
define float @fmul_f(float noundef %a) {
; VENTUS-LABEL: fmul_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(global_val)
; VENTUS-NEXT: lw a0, %lo(global_val)(a0)
; VENTUS-NEXT: vfmul.vf v0, v0, a0
; VENTUS-NEXT: ret
entry:
%val = load float, ptr @global_val, align 4
%mul = fmul float %a, %val
ret float %mul
}
define float @fdiv_v(float noundef %a, float noundef %b) {
; VENTUS-LABEL: fdiv_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfdiv.vv v0, v0, v1
; VENTUS-NEXT: ret
entry:
%div = fdiv float %a, %b
ret float %div
}
define float @fdiv_f(float noundef %a, float noundef %b) {
; VENTUS-LABEL: fdiv_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(global_val)
; VENTUS-NEXT: lw a0, %lo(global_val)(a0)
; VENTUS-NEXT: vfdiv.vf v0, v0, a0
; VENTUS-NEXT: ret
entry:
%val = load float, ptr @global_val, align 4
%div = fdiv float %a, %val
ret float %div
}
define float @foo_constant(float noundef %a) {
; VENTUS-LABEL: foo_constant:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI8_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI8_0)(a0)
; VENTUS-NEXT: vfmul.vf v0, v0, a0
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, 1.25
ret float %mul
}
define float @sqrt_f32(float %a) {
; VENTUS-LABEL: sqrt_f32:
; VENTUS: # %bb.0:
; VENTUS-NEXT: vfsqrt.v v0, v0
; VENTUS-NEXT: ret
%b = call float @llvm.sqrt.f32(float %a)
ret float %b
}
define dso_local float @feq(float noundef %a, float noundef %b) local_unnamed_addr {
; VENTUS-LABEL: feq:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vmv.s.x v2, zero
; VENTUS-NEXT: vmfeq.vv v0, v0, v1
; VENTUS-NEXT: lui a0, %hi(.LCPI10_0)
; VENTUS-NEXT: addi a0, a0, %lo(.LCPI10_0)
; VENTUS-NEXT: vbne v0, v2, .LBB10_2
; VENTUS-NEXT: # %bb.1: # %entry
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB10_3
; VENTUS-NEXT: .LBB10_2: # %entry
; VENTUS-NEXT: addi a0, a0, 4
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB10_3
; VENTUS-NEXT: .LBB10_3: # %entry
; VENTUS-NEXT: vmv.s.x v1, zero
; VENTUS-NEXT: vmv.x.s a0, v0
; VENTUS-NEXT: vluxei32.v v0, (a0), v1
; VENTUS-NEXT: ret
entry:
%cmp = fcmp oeq float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @fneq(float noundef %a, float noundef %b) local_unnamed_addr {
; VENTUS-LABEL: fneq:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vmv.s.x v2, zero
; VENTUS-NEXT: vmfne.vv v0, v0, v1
; VENTUS-NEXT: lui a0, %hi(.LCPI11_0)
; VENTUS-NEXT: addi a0, a0, %lo(.LCPI11_0)
; VENTUS-NEXT: vbne v0, v2, .LBB11_2
; VENTUS-NEXT: # %bb.1: # %entry
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB11_3
; VENTUS-NEXT: .LBB11_2: # %entry
; VENTUS-NEXT: addi a0, a0, 4
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB11_3
; VENTUS-NEXT: .LBB11_3: # %entry
; VENTUS-NEXT: vmv.s.x v1, zero
; VENTUS-NEXT: vmv.x.s a0, v0
; VENTUS-NEXT: vluxei32.v v0, (a0), v1
; VENTUS-NEXT: ret
entry:
%cmp = fcmp une float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @flt(float noundef %a, float noundef %b) local_unnamed_addr {
; VENTUS-LABEL: flt:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vmv.s.x v2, zero
; VENTUS-NEXT: vmflt.vv v0, v0, v1
; VENTUS-NEXT: lui a0, %hi(.LCPI12_0)
; VENTUS-NEXT: addi a0, a0, %lo(.LCPI12_0)
; VENTUS-NEXT: vbne v0, v2, .LBB12_2
; VENTUS-NEXT: # %bb.1: # %entry
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB12_3
; VENTUS-NEXT: .LBB12_2: # %entry
; VENTUS-NEXT: addi a0, a0, 4
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB12_3
; VENTUS-NEXT: .LBB12_3: # %entry
; VENTUS-NEXT: vmv.s.x v1, zero
; VENTUS-NEXT: vmv.x.s a0, v0
; VENTUS-NEXT: vluxei32.v v0, (a0), v1
; VENTUS-NEXT: ret
entry:
%cmp = fcmp olt float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @fle(float noundef %a, float noundef %b) local_unnamed_addr {
; VENTUS-LABEL: fle:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vmv.s.x v2, zero
; VENTUS-NEXT: vmfle.vv v0, v0, v1
; VENTUS-NEXT: lui a0, %hi(.LCPI13_0)
; VENTUS-NEXT: addi a0, a0, %lo(.LCPI13_0)
; VENTUS-NEXT: vbne v0, v2, .LBB13_2
; VENTUS-NEXT: # %bb.1: # %entry
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB13_3
; VENTUS-NEXT: .LBB13_2: # %entry
; VENTUS-NEXT: addi a0, a0, 4
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB13_3
; VENTUS-NEXT: .LBB13_3: # %entry
; VENTUS-NEXT: vmv.s.x v1, zero
; VENTUS-NEXT: vmv.x.s a0, v0
; VENTUS-NEXT: vluxei32.v v0, (a0), v1
; VENTUS-NEXT: ret
entry:
%cmp = fcmp ole float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
; Function Attrs: noinline nounwind optnone
define dso_local float @fgt(float noundef %a) {
; VENTUS-LABEL: fgt:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI14_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI14_0)(a0)
; VENTUS-NEXT: vmv.s.x v1, zero
; VENTUS-NEXT: vmfgt.vf v0, v0, a0
; VENTUS-NEXT: lui a0, %hi(.LCPI14_1)
; VENTUS-NEXT: addi a0, a0, %lo(.LCPI14_1)
; VENTUS-NEXT: vbne v0, v1, .LBB14_2
; VENTUS-NEXT: # %bb.1: # %entry
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB14_3
; VENTUS-NEXT: .LBB14_2: # %entry
; VENTUS-NEXT: addi a0, a0, 4
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB14_3
; VENTUS-NEXT: .LBB14_3: # %entry
; VENTUS-NEXT: vmv.s.x v1, zero
; VENTUS-NEXT: vmv.x.s a0, v0
; VENTUS-NEXT: vluxei32.v v0, (a0), v1
; VENTUS-NEXT: ret
entry:
%b = alloca float, align 4, addrspace(5)
store float 0x3FF3333340000000, ptr addrspace(5) %b, align 4
%0 = load float, ptr addrspace(5) %b, align 4
%cmp = fcmp ogt float %a, %0
%cond = select i1 %cmp, i32 1, i32 0
%conv = sitofp i32 %cond to float
ret float %conv
}
; Function Attrs: noinline nounwind optnone
define dso_local float @fge(float noundef %a) {
; VENTUS-LABEL: fge:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI15_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI15_0)(a0)
; VENTUS-NEXT: vmv.s.x v1, zero
; VENTUS-NEXT: vmfge.vf v0, v0, a0
; VENTUS-NEXT: lui a0, %hi(.LCPI15_1)
; VENTUS-NEXT: addi a0, a0, %lo(.LCPI15_1)
; VENTUS-NEXT: vbne v0, v1, .LBB15_2
; VENTUS-NEXT: # %bb.1: # %entry
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB15_3
; VENTUS-NEXT: .LBB15_2: # %entry
; VENTUS-NEXT: addi a0, a0, 4
; VENTUS-NEXT: vmv.s.x v0, a0
; VENTUS-NEXT: vjoin .LBB15_3
; VENTUS-NEXT: .LBB15_3: # %entry
; VENTUS-NEXT: vmv.s.x v1, zero
; VENTUS-NEXT: vmv.x.s a0, v0
; VENTUS-NEXT: vluxei32.v v0, (a0), v1
; VENTUS-NEXT: ret
entry:
%b = alloca float, align 4, addrspace(5)
store float 0x3FF3333340000000, ptr addrspace(5) %b, align 4
%0 = load float, ptr addrspace(5) %b, align 4
%cmp = fcmp oge float %a, %0
%cond = select i1 %cmp, i32 1, i32 0
%conv = sitofp i32 %cond to float
ret float %conv
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local noundef float @fmadd(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmadd:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, %b
%add = fadd float %mul, %c
ret float %add
}
; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
define dso_local noundef float @fmadd_llvm(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmadd_llvm:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%0 = tail call float @llvm.fmuladd.f32(float %a, float %b, float %c)
ret float %0
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local noundef float @fmsub(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmsub:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmsub.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, %b
%sub = fsub float %mul, %c
ret float %sub
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,2048)
define dso_local i32 @fcvt_x_f(float noundef %a) local_unnamed_addr {
; VENTUS-LABEL: fcvt_x_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfcvt.x.f.v v0, v0
; VENTUS-NEXT: ret
entry:
%conv = fptosi float %a to i32
ret i32 %conv
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,2048)
define dso_local i32 @fcvtu_xu_f(float noundef %a) local_unnamed_addr {
; VENTUS-LABEL: fcvtu_xu_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfcvt.xu.f.v v0, v0
; VENTUS-NEXT: ret
entry:
%conv = fptoui float %a to i32
ret i32 %conv
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,2048)
define dso_local float @fcvt_f_x(i32 noundef %a) local_unnamed_addr {
; VENTUS-LABEL: fcvt_f_x:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfcvt.f.x.v v0, v0
; VENTUS-NEXT: ret
entry:
%conv = sitofp i32 %a to float
ret float %conv
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none) vscale_range(1,2048)
define dso_local float @fcvt_f_xu(i32 noundef %a) local_unnamed_addr {
; VENTUS-LABEL: fcvt_f_xu:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfcvt.f.xu.v v0, v0
; VENTUS-NEXT: ret
entry:
%conv = uitofp i32 %a to float
ret float %conv
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @fmadd_v(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmadd_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, %b
%add = fadd float %mul, %c
ret float %add
}
; Function Attrs: mustprogress nofree nosync nounwind willreturn memory(none)
define dso_local float @fmadd_f(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmadd_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI24_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI24_0)(a0)
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfmadd.vf v0, a0, v2
; VENTUS-NEXT: ret
entry:
%0 = tail call float @llvm.fmuladd.f32(float %b, float 0x3FF3333340000000, float %c)
ret float %0
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @fnmadd_v(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fnmadd_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfnmadd.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%0 = fneg float %a
%fneg = fmul float %0, %b
%sub = fsub float %fneg, %c
ret float %sub
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @fnmadd_f(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fnmadd_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI26_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI26_0)(a0)
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfmsub.vf v0, a0, v2
; VENTUS-NEXT: ret
entry:
%fneg = fmul float %b, 0xBFF3333340000000
%sub = fsub float %fneg, %c
ret float %sub
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @fmsub_v(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fmsub_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfmsub.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, %b
%sub = fsub float %mul, %c
ret float %sub
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @fmsub_f(float noundef %a, float noundef %b) local_unnamed_addr {
; VENTUS-LABEL: fmsub_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI28_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI28_0)(a0)
; VENTUS-NEXT: vfmsub.vf v0, a0, v1
; VENTUS-NEXT: ret
entry:
%mul = fmul float %a, 0x3FF3333340000000
%sub = fsub float %mul, %b
ret float %sub
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @fnmsub_v(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fnmsub_v:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: vfnmsub.vv v0, v1, v2
; VENTUS-NEXT: ret
entry:
%0 = fmul float %a, %b
%add = fsub float %c, %0
ret float %add
}
; Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn memory(none)
define dso_local float @fnmsub_f(float noundef %a, float noundef %b, float noundef %c) local_unnamed_addr {
; VENTUS-LABEL: fnmsub_f:
; VENTUS: # %bb.0: # %entry
; VENTUS-NEXT: lui a0, %hi(.LCPI30_0)
; VENTUS-NEXT: lw a0, %lo(.LCPI30_0)(a0)
; VENTUS-NEXT: vadd.vx v0, v1, zero
; VENTUS-NEXT: vfmadd.vf v0, a0, v2
; VENTUS-NEXT: ret
entry:
%fneg = fmul float %b, 0x3FF3333340000000
%0 = fsub float %c, %fneg
ret float %0
}
; Function Attrs: mustprogress nocallback nofree nosync nounwind speculatable willreturn memory(none)
define float @fsgnj_v(float %a, float %b) nounwind {
; VENTUS-LABEL: fsgnj_v:
; VENTUS: # %bb.0:
; VENTUS-NEXT: vfsgnj.vv v0, v0, v1
; VENTUS-NEXT: ret
%1 = call float @llvm.copysign.f32(float %a, float %b)
ret float %1
}
define float @fsgnjn_v(float %a, float %b) nounwind {
; VENTUS-LABEL: fsgnjn_v:
; VENTUS: # %bb.0:
; VENTUS-NEXT: vfadd.vv v1, v0, v1
; VENTUS-NEXT: vfsgnjn.vv v0, v0, v1
; VENTUS-NEXT: ret
%1 = fadd float %a, %b
%2 = fneg float %1
%3 = call float @llvm.copysign.f32(float %a, float %2)
ret float %3
}
define float @fsgnjn_v_1(float %a) nounwind {
; VENTUS-LABEL: fsgnjn_v_1:
; VENTUS: # %bb.0:
; VENTUS-NEXT: vfsgnjn.vv v0, v0, v0
; VENTUS-NEXT: ret
%1 = fneg float %a
ret float %1
}
define float @fsgnjnx_v(float %a) nounwind {
; VENTUS-LABEL: fsgnjnx_v:
; VENTUS: # %bb.0:
; VENTUS-NEXT: vfsgnjx.vv v0, v0, v0
; VENTUS-NEXT: ret
%1 = call float @llvm.fabs.f32(float %a)
ret float %1
}
define i32 @fcvt_rtz_x_f_v(float %a) nounwind {
; VENTUS-LABEL: fcvt_rtz_x_f_v:
; VENTUS: # %bb.0:
; VENTUS-NEXT: vfcvt.rtz.x.f.v v0, v0
; VENTUS-NEXT: ret
%1 = call float @llvm.trunc.f32(float %a)
%conv = fptosi float %1 to i32
ret i32 %conv
}
define i32 @fcvt_rtz_xu_f_v(float %x) {
; VENTUS-LABEL: fcvt_rtz_xu_f_v:
; VENTUS: # %bb.0:
; VENTUS-NEXT: vfcvt.rtz.xu.f.v v0, v0
; VENTUS-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
%b = fptoui float %a to i32
ret i32 %b
}
@global_val = dso_local global float 0x3FF547AE20000000, align 4
declare float @llvm.sqrt.f32(float %Val)
declare float @llvm.fmuladd.f32(float, float, float)
declare float @llvm.trunc.f32(float)
declare float @llvm.fabs.f32(float %Val)
declare float @llvm.copysign.f32(float %a, float %b)
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