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Andrew Savonichev e6ce0db378 [MCA] Ensure that writes occur in-order 
Delay the issue of a new instruction if that leads to out-of-order
commits of writes.

This patch fixes the problem described in:
https://bugs.llvm.org/show_bug.cgi?id=41796#c3

Differential Revision: https://reviews.llvm.org/D98604
 		2021-03-18 17:10:20 +03:00
..
HardwareUnits [MCA] Support in-order CPUs with MicroOpBufferSize=1 2021-03-11 10:12:54 +00:00
Stages [MCA] Ensure that writes occur in-order 2021-03-18 17:10:20 +03:00
CMakeLists.txt [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
CodeEmitter.cpp [MC][Bugfix] Remove redundant parameter for relaxInstruction 2020-04-21 11:06:55 +08:00
Context.cpp [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
HWEventListener.cpp
…
InstrBuilder.cpp [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
Instruction.cpp
…
Pipeline.cpp Revert "Remove redundant "std::move"s in return statements" 2020-02-10 07:07:40 -08:00
Support.cpp
…