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AsmParser
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[AArch64] Parse "rng" feature flag in .arch directive
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2021-03-16 14:10:19 -07:00 |
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Disassembler
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[AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension
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2020-12-17 13:46:23 +00:00 |
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GISel
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GlobalISel: Preserve source value information for outgoing byval args
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2021-03-18 09:16:54 -04:00 |
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MCTargetDesc
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[MC][AArch64] Support .reloc *, BFD_RELOC_{NONE,16,32,64}, *
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2021-03-05 21:31:08 -08:00 |
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TargetInfo
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llvmbuildectomy - replace llvm-build by plain cmake
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2020-11-13 10:35:24 +01:00 |
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Utils
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[ARM][AArch64] Adding basic support for the v8.7-A architecture
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2020-12-17 13:45:08 +00:00 |
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AArch64.h
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[AArch64] Homogeneous Prolog and Epilog Size Optimization
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2021-02-02 14:57:26 -08:00 |
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AArch64.td
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[AArch64] Add some missing Neoverse features
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2021-02-19 09:18:35 +00:00 |
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AArch64A53Fix835769.cpp
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AArch64A57FPLoadBalancing.cpp
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AArch64AdvSIMDScalarPass.cpp
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[AArch64] Update a code comment incorrectly referring to zero_reg. NFC
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2020-08-20 14:36:59 +02:00 |
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AArch64AsmPrinter.cpp
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[DebugInfo] Handle DBG_VALUES with multiple variable location operands in MIR
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2021-03-10 17:15:24 +00:00 |
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AArch64BranchTargets.cpp
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[AArch64] PAC/BTI code generation for LLVM generated functions
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2020-09-25 11:47:14 +01:00 |
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AArch64CallingConvention.cpp
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[SVE] Deal with SVE tuple call arguments correctly when running out of registers
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2020-11-12 08:41:50 +00:00 |
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AArch64CallingConvention.h
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AArch64CallingConvention.td
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AArch64CleanupLocalDynamicTLSPass.cpp
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AArch64CollectLOH.cpp
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[AArch64] Fix emitting an AdrpAddLdr LOH when there's a potential clobber of the
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2021-03-01 13:52:57 -08:00 |
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AArch64Combine.td
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[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
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2021-03-08 13:01:10 -08:00 |
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AArch64CompressJumpTables.cpp
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[AArch64] Don't try to compress jump tables if there are any inline asm instructions.
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2020-12-10 12:20:02 -08:00 |
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AArch64CondBrTuning.cpp
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AArch64ConditionOptimizer.cpp
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AArch64ConditionalCompares.cpp
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AArch64DeadRegisterDefinitionsPass.cpp
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AArch64ExpandImm.cpp
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AArch64ExpandImm.h
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AArch64ExpandPseudoInsts.cpp
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[AArch64] Add implicit uses for operands when expanding BLR_RVMARKER.
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2021-03-03 21:56:05 +00:00 |
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AArch64FalkorHWPFFix.cpp
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Small fixes for "[LoopInfo] empty() -> isInnermost(), add isOutermost()"
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2020-09-22 23:59:34 +03:00 |
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AArch64FastISel.cpp
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AArch64: relax address-space assertion in FastISel.
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2021-02-25 10:15:55 +00:00 |
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AArch64FrameLowering.cpp
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Revert "[AArch64][SVE] Allow accesses to SVE stack objects to use frame pointer"
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2021-03-11 13:32:35 +00:00 |
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AArch64FrameLowering.h
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[AArch64] Homogeneous Prolog and Epilog Size Optimization
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2021-02-02 14:57:26 -08:00 |
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AArch64GenRegisterBankInfo.def
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AArch64ISelDAGToDAG.cpp
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[AArch64] Adding ACLE intrinsics for the LS64 extension
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2021-01-14 09:43:58 +00:00 |
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AArch64ISelLowering.cpp
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[llvm][AArch64][SVE] Lower fixed length vector fabs
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2021-03-18 17:20:08 +00:00 |
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AArch64ISelLowering.h
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[AArch64] Implement __rndr, __rndrrs intrinsics
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2021-03-15 17:51:48 +00:00 |
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AArch64InstrAtomics.td
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AArch64InstrFormats.td
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[AArch64] Implement __rndr, __rndrrs intrinsics
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2021-03-15 17:51:48 +00:00 |
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AArch64InstrGISel.td
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[AArch64][GlobalISel] Add selection support for fpr bank source variants of G_SITOFP and G_UITOFP.
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2021-01-14 19:31:19 -08:00 |
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AArch64InstrInfo.cpp
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Change void getNoop(MCInst &NopInst) to MCInst getNop()
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2021-03-15 12:05:34 -07:00 |
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AArch64InstrInfo.h
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Change void getNoop(MCInst &NopInst) to MCInst getNop()
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2021-03-15 12:05:34 -07:00 |
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AArch64InstrInfo.td
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[AArch64] Rewrite (add, csel) to cinc
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2021-03-18 08:49:27 +00:00 |
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AArch64LoadStoreOptimizer.cpp
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[AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone.
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2021-02-24 09:55:48 -08:00 |
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AArch64LowerHomogeneousPrologEpilog.cpp
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AArch64LowerHomogeneousPrologEpilog.cpp - fix Wdocumentation warning. NFCI.
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2021-02-05 11:34:43 +00:00 |
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AArch64MCInstLower.cpp
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[AArch64] [Windows] Properly add :lo12: reloc specifiers when generating assembly
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2021-01-12 23:56:03 +02:00 |
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AArch64MCInstLower.h
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AArch64MachineFunctionInfo.cpp
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[AArch64] PAC/BTI code generation for LLVM generated functions
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2020-09-25 11:47:14 +01:00 |
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AArch64MachineFunctionInfo.h
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Revert "[AArch64][SVE] Allow accesses to SVE stack objects to use frame pointer"
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2021-03-11 13:32:35 +00:00 |
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AArch64MacroFusion.cpp
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[AArch64] Add Cortex CPU subtarget features for instruction fusion.
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2021-01-25 09:11:29 +00:00 |
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AArch64MacroFusion.h
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[llvm] Add missing header guards (NFC)
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2021-01-30 09:53:42 -08:00 |
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AArch64PBQPRegAlloc.cpp
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AArch64PBQPRegAlloc.h
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AArch64PerfectShuffle.h
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AArch64PfmCounters.td
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AArch64PromoteConstant.cpp
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AArch64RedundantCopyElimination.cpp
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[AArch64] Fix Copy Elemination for negative values
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2020-12-18 13:30:46 +00:00 |
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AArch64RegisterBanks.td
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AArch64RegisterInfo.cpp
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Change materializeFrameBaseRegister() to return register
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2021-01-22 15:51:06 -08:00 |
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AArch64RegisterInfo.h
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Change materializeFrameBaseRegister() to return register
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2021-01-22 15:51:06 -08:00 |
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AArch64RegisterInfo.td
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[AArch64] Add a GPR64x8 register class
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2020-12-17 13:45:46 +00:00 |
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AArch64SIMDInstrOpt.cpp
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[AArch64] reuse another map iterator. NFC
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2020-09-28 11:30:21 -07:00 |
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AArch64SLSHardening.cpp
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AArch64SVEInstrInfo.td
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[AArch64][SVE] Add unpredicated ld1/st1 patterns for reg+reg addressing modes
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2021-03-15 12:36:28 +00:00 |
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AArch64SchedA53.td
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AArch64SchedA55.td
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[MCA] Add support for in-order CPUs
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2021-03-04 14:08:19 +03:00 |
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AArch64SchedA57.td
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[AARCH64] Improve accumulator forwarding for Cortex-A57 model
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2021-01-04 10:58:43 +00:00 |
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AArch64SchedA57WriteRes.td
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[AARCH64] Improve accumulator forwarding for Cortex-A57 model
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2021-01-04 10:58:43 +00:00 |
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AArch64SchedA64FX.td
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[AArch64] Add Fujitsu A64FX scheduling model
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2021-01-15 17:14:04 +09:00 |
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AArch64SchedCyclone.td
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AArch64SchedExynosM3.td
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AArch64SchedExynosM4.td
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AArch64SchedExynosM5.td
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AArch64SchedFalkor.td
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AArch64SchedFalkorDetails.td
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AArch64SchedKryo.td
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AArch64SchedKryoDetails.td
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AArch64SchedPredExynos.td
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AArch64SchedPredicates.td
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AArch64SchedTSV110.td
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[AArch64] Add pipeline model for HiSilicon's TSV110
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2020-11-07 01:23:00 +03:00 |
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AArch64SchedThunderX.td
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AArch64SchedThunderX2T99.td
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AArch64SchedThunderX3T110.td
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AArch64Schedule.td
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AArch64SelectionDAGInfo.cpp
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[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
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2021-02-18 16:55:16 +00:00 |
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AArch64SelectionDAGInfo.h
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[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
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2021-02-18 16:55:16 +00:00 |
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AArch64SpeculationHardening.cpp
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AArch64StackTagging.cpp
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Reapply "[DebugInfo] Handle multiple variable location operands in IR"
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2021-03-17 16:45:25 +00:00 |
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AArch64StackTaggingPreRA.cpp
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[MTE] Pin the tagged base pointer to one of the stack slots.
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2020-10-15 12:50:16 -07:00 |
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AArch64StorePairSuppress.cpp
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AArch64Subtarget.cpp
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AArch64: add apple-a14 as a CPU
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2021-01-19 14:04:53 +00:00 |
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AArch64Subtarget.h
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[AArch64] Add Cortex CPU subtarget features for instruction fusion.
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2021-01-25 09:11:29 +00:00 |
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AArch64SystemOperands.td
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[AArch64] Add +pauth archictecture option, allowing the v8.3a pointer authentication extension.
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2021-01-08 13:21:11 +00:00 |
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AArch64TargetMachine.cpp
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[AArch64][GlobalISel] Enable use of the optsize predicate in the selector.
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2021-03-02 12:55:51 -08:00 |
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AArch64TargetMachine.h
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Support addrspacecast initializers with isNoopAddrSpaceCast
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2020-07-31 10:42:43 -04:00 |
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AArch64TargetObjectFile.cpp
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AArch64TargetObjectFile.h
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AArch64TargetTransformInfo.cpp
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[TTI] Add a Mask to getShuffleCost
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2021-03-17 17:46:26 +00:00 |
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AArch64TargetTransformInfo.h
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[TTI] Add a Mask to getShuffleCost
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2021-03-17 17:46:26 +00:00 |
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CMakeLists.txt
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[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
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2021-03-08 13:01:10 -08:00 |
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SVEInstrFormats.td
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[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
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2021-02-18 16:55:16 +00:00 |
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SVEIntrinsicOpts.cpp
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[AArch64][SVEIntrinsicOpts] Factor out redundant SVE mul/fmul intrinsics
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2021-03-16 14:50:17 +00:00 |
