Stanislav Mekhanoshin 3bffb1cd0e [AMDGPU] Use single cache policy operand ... Replace individual operands GLC, SLC, and DLC with a single cache_policy bitmask operand. This will reduce the number of operands in MIR and I hope the amount of code. These operands are mostly 0 anyway. Additional advantage that parser will accept these flags in any order unlike now. Differential Revision: https://reviews.llvm.org/D96469		2021-03-15 13:00:59 -07:00
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AMDGPUDisassembler.cpp	[AMDGPU] Use single cache policy operand	2021-03-15 13:00:59 -07:00
AMDGPUDisassembler.h	[AMDGPU] gfx90a support	2021-02-17 16:01:32 -08:00
CMakeLists.txt	llvmbuildectomy - replace llvm-build by plain cmake	2020-11-13 10:35:24 +01:00