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llvm-project/llvm/test/CodeGen
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Thomas Lively 8638c897f4 [WebAssembly] Remove unimplemented-simd target feature 
Now that the WebAssembly SIMD specification is finalized and engines are
generally up-to-date, there is no need for a separate target feature for gating
SIMD instructions that engines have not implemented. With this change,
v128.const is now enabled by default with the simd128 target feature.

Differential Revision: https://reviews.llvm.org/D98457
 		2021-03-18 10:23:12 -07:00
..
AArch64 [llvm][AArch64][SVE] Lower fixed length vector fabs 2021-03-18 17:20:08 +00:00
AMDGPU [amdgpu] Update med3 combine to skip i64 2021-03-18 15:56:41 +00:00
ARC
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ARM [ARM] Regenerate select-imm.ll tests 2021-03-18 11:07:16 +00:00
AVR [AVR] Fix lifeness issues in the AVR backend 2021-03-04 14:04:39 +01:00
BPF [BPF] Add support for floats and doubles 2021-03-05 15:10:11 +01:00
Generic [XCore] Remove XFAIL: xcore from passing test. 2021-03-18 15:46:24 +00:00
Hexagon [Hexagon] Add support for named registers cs0 and cs1 2021-03-18 09:53:22 -05:00
Inputs
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Lanai
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M68k [M68k] Fixed incorrect `extract-section` command substitution 2021-03-16 13:37:50 -07:00
MIR [AMDGPU] Use single cache policy operand 2021-03-15 13:00:59 -07:00
MSP430
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Mips Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
NVPTX [NVPTX] CUDA does provide malloc/free since compute capability 2.X 2021-03-15 22:45:56 -05:00
PowerPC [NFC] [XCOFF] Update PowerPC readobj test case with expression 2021-03-17 16:02:50 +08:00
RISCV [RISCV] Support scalable-vector masked scatter operations 2021-03-18 10:17:50 +00:00
SPARC [LegalizeTypes] Improve ExpandIntRes_XMULO codegen. 2021-03-01 09:54:32 -08:00
SystemZ [SystemZ] Reimplement the i8/i16 compare-and-swap logic. 2021-03-03 14:04:32 -06:00
Thumb [ARM] Use lrdsb for more thumb1 loads. 2021-03-17 15:29:02 +00:00
Thumb2 Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
VE [test] Fix CodeGen/VE/Scalar tests 2021-03-02 15:30:44 -08:00
WebAssembly [WebAssembly] Remove unimplemented-simd target feature 2021-03-18 10:23:12 -07:00
WinCFGuard
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WinEH
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X86 [DAG] Improve folding (sext_in_reg (*_extend_vector_inreg x)) -> (sext_vector_inreg x) 2021-03-18 15:34:53 +00:00
XCore [CodeGen] Report a normal instead of fatal error for label redefinition 2021-03-09 10:54:41 +00:00