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llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex
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Andrew Savonichev e6ce0db378 [MCA] Ensure that writes occur in-order 
Delay the issue of a new instruction if that leads to out-of-order
commits of writes.

This patch fixes the problem described in:
https://bugs.llvm.org/show_bug.cgi?id=41796#c3

Differential Revision: https://reviews.llvm.org/D98604
 		2021-03-18 17:10:20 +03:00
..
A55-add-sequence.s [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
A55-all-stats.s [MCA] Ensure that writes occur in-order 2021-03-18 17:10:20 +03:00
A55-all-views.s [MCA] Ensure that writes occur in-order 2021-03-18 17:10:20 +03:00
A55-basic-instructions.s
…
A55-in-order-retire.s [MCA] Ensure that writes occur in-order 2021-03-18 17:10:20 +03:00
A55-out-of-order-retire.s [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
direct-branch.s
…
forwarding-A57.s [AArch64] Attempt to fix Mac tests with a more specific triple. NFC 2021-01-04 11:29:18 +00:00
in-order-bottleneck-analysis.s [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
shifted-register.s
…