d791695cb5
This patch adds a pipeline to support in-order CPUs such as ARM Cortex-A55. In-order pipeline implements a simplified version of Dispatch, Scheduler and Execute stages as a single stage. Entry and Retire stages are common for both in-order and out-of-order pipelines. Differential Revision: https://reviews.llvm.org/D94928 |
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| .. | ||
| cortex-a57-basic-instructions.s | ||
| cortex-a57-memory-instructions.s | ||
| cortex-a57-neon-instructions.s | ||
| cortex-a57-thumb.s | ||
| lit.local.cfg | ||
| m4-int.s | ||
| m4-targetfeatures.s | ||
| m7-fp.s | ||
| m7-int.s | ||
| m7-negative-readadvance.s | ||
| memcpy-ldm-stm.s | ||
| simple-cortex-m33.s | ||
| simple-test-cortex-a9.s | ||
| unsupported-write-variant.s | ||
| vld1-index-update.s | ||