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Jessica Clarke 616289ed29 [LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG 
Summary:
Currently, the comparison argument used for ATOMIC_CMP_XCHG is legalised
with GetPromotedInteger, which leaves the upper bits of the value
undefind. Since this is used for comparing in an LR/SC loop with a
full-width comparison, we must sign extend it. We introduce a new
getExtendForAtomicCmpSwapArg to complement getExtendForAtomicOps, since
many targets have compare-and-swap instructions (or pseudos) that
correctly handle an any-extend input, and the existing function
determines the extension of the result, whereas we are concerned with
the input.

This is related to https://reviews.llvm.org/D58829, which solved the
issue for ATOMIC_CMP_SWAP_WITH_SUCCESS, but not the simpler
ATOMIC_CMP_SWAP.

Reviewers: asb, lenary, efriedma

Reviewed By: asb

Subscribers: arichardson, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, luismarques, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74453
 		2020-04-01 15:51:26 +01:00
..
AsmParser [RISCV] ELF attribute section for RISC-V. 2020-03-31 16:16:19 +08:00
Disassembler CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
MCTargetDesc [RISCV] ELF attribute section for RISC-V. 2020-03-31 16:16:19 +08:00
TargetInfo CMake: Make most target symbols hidden by default 2020-01-14 19:46:52 -08:00
Utils [RISCV] Support ABI checking with per function target-features 2020-01-22 08:12:28 -08:00
CMakeLists.txt [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
LLVMBuild.txt [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCV.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCV.td [TableGen] Support combining AssemblerPredicates with ORs 2020-03-13 17:13:51 +00:00
RISCVAsmPrinter.cpp [RISCV] ELF attribute section for RISC-V. 2020-03-31 16:16:19 +08:00
RISCVCallLowering.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVCallLowering.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVCallingConv.td [RISCV] Rename FPRs and use Register arithmetic 2019-09-27 15:49:10 +00:00
RISCVExpandPseudoInsts.cpp [RISCV] Use addi rather than add x0 2019-11-14 18:43:38 +00:00
RISCVFrameLowering.cpp [Alignment][NFC] Use TFL::getStackAlign() 2020-03-23 13:48:29 +01:00
RISCVFrameLowering.h ArrayRef'ize restoreCalleeSavedRegisters. NFCI. 2020-02-29 09:50:23 +01:00
RISCVISelDAGToDAG.cpp [RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp 2020-04-01 11:30:21 +08:00
RISCVISelDAGToDAG.h [RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp 2020-04-01 11:30:21 +08:00
RISCVISelLowering.cpp [Alignment][NFC] Use Align version of getMachineMemOperand 2020-03-30 15:46:27 +00:00
RISCVISelLowering.h [LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG 2020-04-01 15:51:26 +01:00
RISCVInstrFormats.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstrFormatsC.td
…
RISCVInstrInfo.cpp [NFC] unsigned->Register in storeRegTo/loadRegFromStack 2020-02-03 14:22:16 +01:00
RISCVInstrInfo.h [NFC] unsigned->Register in storeRegTo/loadRegFromStack 2020-02-03 14:22:16 +01:00
RISCVInstrInfo.td [RISCV] Add new SchedRead SchedWrite 2020-03-10 00:12:27 +08:00
RISCVInstrInfoA.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstrInfoC.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstrInfoD.td [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w 2020-03-20 09:42:24 +00:00
RISCVInstrInfoF.td [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w 2020-03-20 09:42:24 +00:00
RISCVInstrInfoM.td [RISCV] Scheduler description for the Rocket core 2020-01-23 19:36:47 -06:00
RISCVInstructionSelector.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.cpp [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVMCInstLower.cpp [RISCV] Add lowering of global TLS addresses 2019-06-19 08:40:59 +00:00
RISCVMachineFunctionInfo.h [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
RISCVMergeBaseOffset.cpp [RISCV] Convert registers from unsigned to Register 2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes" 2020-03-20 11:02:50 +01:00
RISCVRegisterBankInfo.h Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes" 2020-03-20 11:02:50 +01:00
RISCVRegisterBanks.td [RISCV GlobalISel] Adding initial GlobalISel infrastructure 2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp [RISCV] Correct the CallPreservedMask for the function call in an interrupt handler 2020-02-15 09:14:04 +08:00
RISCVRegisterInfo.h [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
RISCVRegisterInfo.td [RISCV] Rename FPRs and use Register arithmetic 2019-09-27 15:49:10 +00:00
RISCVSchedRocket32.td [RISCV] Add new SchedRead SchedWrite 2020-03-10 00:12:27 +08:00
RISCVSchedRocket64.td [RISCV] Add new SchedRead SchedWrite 2020-03-10 00:12:27 +08:00
RISCVSchedule.td [RISCV] Add new SchedRead SchedWrite 2020-03-10 00:12:27 +08:00
RISCVSubtarget.cpp Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes" 2020-03-20 11:02:50 +01:00
RISCVSubtarget.h [RISCV] Add support for save/restore of callee-saved registers via libcalls 2020-02-11 21:23:03 +00:00
RISCVSystemOperands.td [RISCV][NFC] Replace hard-coded CSR duplication with symbolic references 2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp [RISCV] Check the target-abi module flag matches the option 2020-01-21 07:32:12 -08:00
RISCVTargetMachine.h [RISCV] Add subtargets initialized with target feature 2019-12-17 09:34:01 -08:00
RISCVTargetObjectFile.cpp [X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile 2020-03-20 21:57:34 -07:00
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp Rename TTI::getIntImmCost for instructions and intrinsics 2019-12-11 18:00:20 -08:00
RISCVTargetTransformInfo.h Rename TTI::getIntImmCost for instructions and intrinsics 2019-12-11 18:00:20 -08:00