734 lines
22 KiB
Plaintext
734 lines
22 KiB
Plaintext
//===---------------------------------------------------------------------===//
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// Random ideas for the ARM backend.
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//===---------------------------------------------------------------------===//
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Reimplement 'select' in terms of 'SEL'.
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* We would really like to support UXTAB16, but we need to prove that the
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add doesn't need to overflow between the two 16-bit chunks.
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* Implement pre/post increment support. (e.g. PR935)
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* Implement smarter constant generation for binops with large immediates.
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A few ARMv6T2 ops should be pattern matched: BFI, SBFX, and UBFX
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Interesting optimization for PIC codegen on arm-linux:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43129
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//===---------------------------------------------------------------------===//
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Crazy idea: Consider code that uses lots of 8-bit or 16-bit values. By the
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time regalloc happens, these values are now in a 32-bit register, usually with
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the top-bits known to be sign or zero extended. If spilled, we should be able
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to spill these to a 8-bit or 16-bit stack slot, zero or sign extending as part
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of the reload.
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Doing this reduces the size of the stack frame (important for thumb etc), and
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also increases the likelihood that we will be able to reload multiple values
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from the stack with a single load.
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//===---------------------------------------------------------------------===//
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The constant island pass is in good shape. Some cleanups might be desirable,
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but there is unlikely to be much improvement in the generated code.
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1. There may be some advantage to trying to be smarter about the initial
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placement, rather than putting everything at the end.
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2. There might be some compile-time efficiency to be had by representing
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consecutive islands as a single block rather than multiple blocks.
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3. Use a priority queue to sort constant pool users in inverse order of
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position so we always process the one closed to the end of functions
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first. This may simply CreateNewWater.
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//===---------------------------------------------------------------------===//
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Eliminate copysign custom expansion. We are still generating crappy code with
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default expansion + if-conversion.
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//===---------------------------------------------------------------------===//
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Eliminate one instruction from:
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define i32 @_Z6slow4bii(i32 %x, i32 %y) {
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%tmp = icmp sgt i32 %x, %y
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%retval = select i1 %tmp, i32 %x, i32 %y
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ret i32 %retval
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}
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__Z6slow4bii:
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cmp r0, r1
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movgt r1, r0
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mov r0, r1
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bx lr
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=>
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__Z6slow4bii:
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cmp r0, r1
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movle r0, r1
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bx lr
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//===---------------------------------------------------------------------===//
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Implement long long "X-3" with instructions that fold the immediate in. These
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were disabled due to badness with the ARM carry flag on subtracts.
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//===---------------------------------------------------------------------===//
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More load / store optimizations:
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1) Better representation for block transfer? This is from Olden/power:
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fldd d0, [r4]
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fstd d0, [r4, #+32]
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fldd d0, [r4, #+8]
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fstd d0, [r4, #+40]
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fldd d0, [r4, #+16]
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fstd d0, [r4, #+48]
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fldd d0, [r4, #+24]
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fstd d0, [r4, #+56]
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If we can spare the registers, it would be better to use fldm and fstm here.
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Need major register allocator enhancement though.
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2) Can we recognize the relative position of constantpool entries? i.e. Treat
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ldr r0, LCPI17_3
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ldr r1, LCPI17_4
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ldr r2, LCPI17_5
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as
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ldr r0, LCPI17
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ldr r1, LCPI17+4
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ldr r2, LCPI17+8
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Then the ldr's can be combined into a single ldm. See Olden/power.
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Note for ARM v4 gcc uses ldmia to load a pair of 32-bit values to represent a
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double 64-bit FP constant:
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adr r0, L6
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ldmia r0, {r0-r1}
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.align 2
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L6:
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.long -858993459
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.long 1074318540
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3) struct copies appear to be done field by field
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instead of by words, at least sometimes:
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struct foo { int x; short s; char c1; char c2; };
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void cpy(struct foo*a, struct foo*b) { *a = *b; }
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llvm code (-O2)
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ldrb r3, [r1, #+6]
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ldr r2, [r1]
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ldrb r12, [r1, #+7]
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ldrh r1, [r1, #+4]
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str r2, [r0]
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strh r1, [r0, #+4]
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strb r3, [r0, #+6]
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strb r12, [r0, #+7]
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gcc code (-O2)
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ldmia r1, {r1-r2}
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stmia r0, {r1-r2}
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In this benchmark poor handling of aggregate copies has shown up as
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having a large effect on size, and possibly speed as well (we don't have
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a good way to measure on ARM).
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//===---------------------------------------------------------------------===//
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* Consider this silly example:
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double bar(double x) {
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double r = foo(3.1);
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return x+r;
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}
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_bar:
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stmfd sp!, {r4, r5, r7, lr}
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add r7, sp, #8
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mov r4, r0
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mov r5, r1
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fldd d0, LCPI1_0
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fmrrd r0, r1, d0
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bl _foo
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fmdrr d0, r4, r5
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fmsr s2, r0
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fsitod d1, s2
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faddd d0, d1, d0
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fmrrd r0, r1, d0
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ldmfd sp!, {r4, r5, r7, pc}
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Ignore the prologue and epilogue stuff for a second. Note
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mov r4, r0
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mov r5, r1
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the copys to callee-save registers and the fact they are only being used by the
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fmdrr instruction. It would have been better had the fmdrr been scheduled
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before the call and place the result in a callee-save DPR register. The two
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mov ops would not have been necessary.
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//===---------------------------------------------------------------------===//
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Calling convention related stuff:
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* gcc's parameter passing implementation is terrible and we suffer as a result:
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e.g.
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struct s {
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double d1;
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int s1;
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};
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void foo(struct s S) {
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printf("%g, %d\n", S.d1, S.s1);
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}
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'S' is passed via registers r0, r1, r2. But gcc stores them to the stack, and
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then reload them to r1, r2, and r3 before issuing the call (r0 contains the
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address of the format string):
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stmfd sp!, {r7, lr}
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add r7, sp, #0
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sub sp, sp, #12
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stmia sp, {r0, r1, r2}
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ldmia sp, {r1-r2}
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ldr r0, L5
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ldr r3, [sp, #8]
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L2:
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add r0, pc, r0
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bl L_printf$stub
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Instead of a stmia, ldmia, and a ldr, wouldn't it be better to do three moves?
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* Return an aggregate type is even worse:
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e.g.
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struct s foo(void) {
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struct s S = {1.1, 2};
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return S;
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}
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mov ip, r0
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ldr r0, L5
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sub sp, sp, #12
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L2:
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add r0, pc, r0
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@ lr needed for prologue
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ldmia r0, {r0, r1, r2}
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stmia sp, {r0, r1, r2}
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stmia ip, {r0, r1, r2}
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mov r0, ip
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add sp, sp, #12
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bx lr
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r0 (and later ip) is the hidden parameter from caller to store the value in. The
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first ldmia loads the constants into r0, r1, r2. The last stmia stores r0, r1,
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r2 into the address passed in. However, there is one additional stmia that
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stores r0, r1, and r2 to some stack location. The store is dead.
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The llvm-gcc generated code looks like this:
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csretcc void %foo(%struct.s* %agg.result) {
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entry:
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%S = alloca %struct.s, align 4 ; <%struct.s*> [#uses=1]
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%memtmp = alloca %struct.s ; <%struct.s*> [#uses=1]
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cast %struct.s* %S to sbyte* ; <sbyte*>:0 [#uses=2]
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call void %llvm.memcpy.i32( sbyte* %0, sbyte* cast ({ double, int }* %C.0.904 to sbyte*), uint 12, uint 4 )
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cast %struct.s* %agg.result to sbyte* ; <sbyte*>:1 [#uses=2]
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call void %llvm.memcpy.i32( sbyte* %1, sbyte* %0, uint 12, uint 0 )
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cast %struct.s* %memtmp to sbyte* ; <sbyte*>:2 [#uses=1]
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call void %llvm.memcpy.i32( sbyte* %2, sbyte* %1, uint 12, uint 0 )
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ret void
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}
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llc ends up issuing two memcpy's (the first memcpy becomes 3 loads from
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constantpool). Perhaps we should 1) fix llvm-gcc so the memcpy is translated
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into a number of load and stores, or 2) custom lower memcpy (of small size) to
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be ldmia / stmia. I think option 2 is better but the current register
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allocator cannot allocate a chunk of registers at a time.
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A feasible temporary solution is to use specific physical registers at the
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lowering time for small (<= 4 words?) transfer size.
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* ARM CSRet calling convention requires the hidden argument to be returned by
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the callee.
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//===---------------------------------------------------------------------===//
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We can definitely do a better job on BB placements to eliminate some branches.
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It's very common to see llvm generated assembly code that looks like this:
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LBB3:
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...
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LBB4:
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...
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beq LBB3
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b LBB2
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If BB4 is the only predecessor of BB3, then we can emit BB3 after BB4. We can
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then eliminate beq and and turn the unconditional branch to LBB2 to a bne.
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See McCat/18-imp/ComputeBoundingBoxes for an example.
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//===---------------------------------------------------------------------===//
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Pre-/post- indexed load / stores:
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1) We should not make the pre/post- indexed load/store transform if the base ptr
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is guaranteed to be live beyond the load/store. This can happen if the base
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ptr is live out of the block we are performing the optimization. e.g.
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mov r1, r2
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ldr r3, [r1], #4
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...
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vs.
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ldr r3, [r2]
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add r1, r2, #4
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...
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In most cases, this is just a wasted optimization. However, sometimes it can
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negatively impact the performance because two-address code is more restrictive
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when it comes to scheduling.
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Unfortunately, liveout information is currently unavailable during DAG combine
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time.
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2) Consider spliting a indexed load / store into a pair of add/sub + load/store
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to solve #1 (in TwoAddressInstructionPass.cpp).
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3) Enhance LSR to generate more opportunities for indexed ops.
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4) Once we added support for multiple result patterns, write indexed loads
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patterns instead of C++ instruction selection code.
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5) Use VLDM / VSTM to emulate indexed FP load / store.
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//===---------------------------------------------------------------------===//
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Implement support for some more tricky ways to materialize immediates. For
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example, to get 0xffff8000, we can use:
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mov r9, #&3f8000
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sub r9, r9, #&400000
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//===---------------------------------------------------------------------===//
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We sometimes generate multiple add / sub instructions to update sp in prologue
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and epilogue if the inc / dec value is too large to fit in a single immediate
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operand. In some cases, perhaps it might be better to load the value from a
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constantpool instead.
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//===---------------------------------------------------------------------===//
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GCC generates significantly better code for this function.
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int foo(int StackPtr, unsigned char *Line, unsigned char *Stack, int LineLen) {
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int i = 0;
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if (StackPtr != 0) {
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while (StackPtr != 0 && i < (((LineLen) < (32768))? (LineLen) : (32768)))
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Line[i++] = Stack[--StackPtr];
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if (LineLen > 32768)
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{
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while (StackPtr != 0 && i < LineLen)
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{
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i++;
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--StackPtr;
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}
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}
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}
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return StackPtr;
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}
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//===---------------------------------------------------------------------===//
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This should compile to the mlas instruction:
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int mlas(int x, int y, int z) { return ((x * y + z) < 0) ? 7 : 13; }
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//===---------------------------------------------------------------------===//
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At some point, we should triage these to see if they still apply to us:
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=19598
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18560
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=27016
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11831
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11826
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11825
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11824
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11823
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=11820
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10982
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=10242
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9831
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9760
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9759
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9703
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9702
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http://gcc.gnu.org/bugzilla/show_bug.cgi?id=9663
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http://www.inf.u-szeged.hu/gcc-arm/
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http://citeseer.ist.psu.edu/debus04linktime.html
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//===---------------------------------------------------------------------===//
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gcc generates smaller code for this function at -O2 or -Os:
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void foo(signed char* p) {
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if (*p == 3)
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bar();
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else if (*p == 4)
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baz();
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else if (*p == 5)
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quux();
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}
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llvm decides it's a good idea to turn the repeated if...else into a
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binary tree, as if it were a switch; the resulting code requires -1
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compare-and-branches when *p<=2 or *p==5, the same number if *p==4
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or *p>6, and +1 if *p==3. So it should be a speed win
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(on balance). However, the revised code is larger, with 4 conditional
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branches instead of 3.
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More seriously, there is a byte->word extend before
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each comparison, where there should be only one, and the condition codes
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are not remembered when the same two values are compared twice.
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//===---------------------------------------------------------------------===//
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More LSR enhancements possible:
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1. Teach LSR about pre- and post- indexed ops to allow iv increment be merged
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in a load / store.
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2. Allow iv reuse even when a type conversion is required. For example, i8
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and i32 load / store addressing modes are identical.
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//===---------------------------------------------------------------------===//
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This:
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int foo(int a, int b, int c, int d) {
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long long acc = (long long)a * (long long)b;
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acc += (long long)c * (long long)d;
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return (int)(acc >> 32);
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}
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Should compile to use SMLAL (Signed Multiply Accumulate Long) which multiplies
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two signed 32-bit values to produce a 64-bit value, and accumulates this with
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a 64-bit value.
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We currently get this with both v4 and v6:
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_foo:
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smull r1, r0, r1, r0
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smull r3, r2, r3, r2
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adds r3, r3, r1
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adc r0, r2, r0
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bx lr
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//===---------------------------------------------------------------------===//
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This:
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#include <algorithm>
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std::pair<unsigned, bool> full_add(unsigned a, unsigned b)
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{ return std::make_pair(a + b, a + b < a); }
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bool no_overflow(unsigned a, unsigned b)
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{ return !full_add(a, b).second; }
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Should compile to:
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_Z8full_addjj:
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adds r2, r1, r2
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movcc r1, #0
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movcs r1, #1
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str r2, [r0, #0]
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strb r1, [r0, #4]
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mov pc, lr
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_Z11no_overflowjj:
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cmn r0, r1
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movcs r0, #0
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movcc r0, #1
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mov pc, lr
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not:
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__Z8full_addjj:
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add r3, r2, r1
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str r3, [r0]
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mov r2, #1
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mov r12, #0
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cmp r3, r1
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movlo r12, r2
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str r12, [r0, #+4]
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bx lr
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__Z11no_overflowjj:
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add r3, r1, r0
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mov r2, #1
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mov r1, #0
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cmp r3, r0
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movhs r1, r2
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mov r0, r1
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bx lr
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//===---------------------------------------------------------------------===//
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Some of the NEON intrinsics may be appropriate for more general use, either
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as target-independent intrinsics or perhaps elsewhere in the ARM backend.
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Some of them may also be lowered to target-independent SDNodes, and perhaps
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some new SDNodes could be added.
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For example, maximum, minimum, and absolute value operations are well-defined
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and standard operations, both for vector and scalar types.
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The current NEON-specific intrinsics for count leading zeros and count one
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bits could perhaps be replaced by the target-independent ctlz and ctpop
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intrinsics. It may also make sense to add a target-independent "ctls"
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intrinsic for "count leading sign bits". Likewise, the backend could use
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the target-independent SDNodes for these operations.
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ARMv6 has scalar saturating and halving adds and subtracts. The same
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intrinsics could possibly be used for both NEON's vector implementations of
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those operations and the ARMv6 scalar versions.
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//===---------------------------------------------------------------------===//
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Split out LDR (literal) from normal ARM LDR instruction. Also consider spliting
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LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
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ARMLoadStoreOptimizer does not need to look at LDR (literal) and LDR (so_reg)
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while ARMConstantIslandPass only need to worry about LDR (literal).
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|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Constant island pass should make use of full range SoImm values for LEApcrel.
|
|
Be careful though as the last attempt caused infinite looping on lencod.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Predication issue. This function:
|
|
|
|
extern unsigned array[ 128 ];
|
|
int foo( int x ) {
|
|
int y;
|
|
y = array[ x & 127 ];
|
|
if ( x & 128 )
|
|
y = 123456789 & ( y >> 2 );
|
|
else
|
|
y = 123456789 & y;
|
|
return y;
|
|
}
|
|
|
|
compiles to:
|
|
|
|
_foo:
|
|
and r1, r0, #127
|
|
ldr r2, LCPI1_0
|
|
ldr r2, [r2]
|
|
ldr r1, [r2, +r1, lsl #2]
|
|
mov r2, r1, lsr #2
|
|
tst r0, #128
|
|
moveq r2, r1
|
|
ldr r0, LCPI1_1
|
|
and r0, r2, r0
|
|
bx lr
|
|
|
|
It would be better to do something like this, to fold the shift into the
|
|
conditional move:
|
|
|
|
and r1, r0, #127
|
|
ldr r2, LCPI1_0
|
|
ldr r2, [r2]
|
|
ldr r1, [r2, +r1, lsl #2]
|
|
tst r0, #128
|
|
movne r1, r1, lsr #2
|
|
ldr r0, LCPI1_1
|
|
and r0, r1, r0
|
|
bx lr
|
|
|
|
it saves an instruction and a register.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
It might be profitable to cse MOVi16 if there are lots of 32-bit immediates
|
|
with the same bottom half.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Robert Muth started working on an alternate jump table implementation that
|
|
does not put the tables in-line in the text. This is more like the llvm
|
|
default jump table implementation. This might be useful sometime. Several
|
|
revisions of patches are on the mailing list, beginning at:
|
|
http://lists.cs.uiuc.edu/pipermail/llvmdev/2009-June/022763.html
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Make use of the "rbit" instruction.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Take a look at test/CodeGen/Thumb2/machine-licm.ll. ARM should be taught how
|
|
to licm and cse the unnecessary load from cp#1.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
The CMN instruction sets the flags like an ADD instruction, while CMP sets
|
|
them like a subtract. Therefore to be able to use CMN for comparisons other
|
|
than the Z bit, we'll need additional logic to reverse the conditionals
|
|
associated with the comparison. Perhaps a pseudo-instruction for the comparison,
|
|
with a post-codegen pass to clean up and handle the condition codes?
|
|
See PR5694 for testcase.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Given the following on armv5:
|
|
int test1(int A, int B) {
|
|
return (A&-8388481)|(B&8388480);
|
|
}
|
|
|
|
We currently generate:
|
|
ldr r2, .LCPI0_0
|
|
and r0, r0, r2
|
|
ldr r2, .LCPI0_1
|
|
and r1, r1, r2
|
|
orr r0, r1, r0
|
|
bx lr
|
|
|
|
We should be able to replace the second ldr+and with a bic (i.e. reuse the
|
|
constant which was already loaded). Not sure what's necessary to do that.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
The code generated for bswap on armv4/5 (CPUs without rev) is less than ideal:
|
|
|
|
int a(int x) { return __builtin_bswap32(x); }
|
|
|
|
a:
|
|
mov r1, #255, 24
|
|
mov r2, #255, 16
|
|
and r1, r1, r0, lsr #8
|
|
and r2, r2, r0, lsl #8
|
|
orr r1, r1, r0, lsr #24
|
|
orr r0, r2, r0, lsl #24
|
|
orr r0, r0, r1
|
|
bx lr
|
|
|
|
Something like the following would be better (fewer instructions/registers):
|
|
eor r1, r0, r0, ror #16
|
|
bic r1, r1, #0xff0000
|
|
mov r1, r1, lsr #8
|
|
eor r0, r1, r0, ror #8
|
|
bx lr
|
|
|
|
A custom Thumb version would also be a slight improvement over the generic
|
|
version.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Consider the following simple C code:
|
|
|
|
void foo(unsigned char *a, unsigned char *b, int *c) {
|
|
if ((*a | *b) == 0) *c = 0;
|
|
}
|
|
|
|
currently llvm-gcc generates something like this (nice branchless code I'd say):
|
|
|
|
ldrb r0, [r0]
|
|
ldrb r1, [r1]
|
|
orr r0, r1, r0
|
|
tst r0, #255
|
|
moveq r0, #0
|
|
streq r0, [r2]
|
|
bx lr
|
|
|
|
Note that both "tst" and "moveq" are redundant.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
When loading immediate constants with movt/movw, if there are multiple
|
|
constants needed with the same low 16 bits, and those values are not live at
|
|
the same time, it would be possible to use a single movw instruction, followed
|
|
by multiple movt instructions to rewrite the high bits to different values.
|
|
For example:
|
|
|
|
volatile store i32 -1, i32* inttoptr (i32 1342210076 to i32*), align 4,
|
|
!tbaa
|
|
!0
|
|
volatile store i32 -1, i32* inttoptr (i32 1342341148 to i32*), align 4,
|
|
!tbaa
|
|
!0
|
|
|
|
is compiled and optimized to:
|
|
|
|
movw r0, #32796
|
|
mov.w r1, #-1
|
|
movt r0, #20480
|
|
str r1, [r0]
|
|
movw r0, #32796 @ <= this MOVW is not needed, value is there already
|
|
movt r0, #20482
|
|
str r1, [r0]
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Improve codegen for select's:
|
|
if (x != 0) x = 1
|
|
if (x == 1) x = 1
|
|
|
|
ARM codegen used to look like this:
|
|
mov r1, r0
|
|
cmp r1, #1
|
|
mov r0, #0
|
|
moveq r0, #1
|
|
|
|
The naive lowering select between two different values. It should recognize the
|
|
test is equality test so it's more a conditional move rather than a select:
|
|
cmp r0, #1
|
|
movne r0, #0
|
|
|
|
Currently this is a ARM specific dag combine. We probably should make it into a
|
|
target-neutral one.
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Optimize unnecessary checks for zero with __builtin_clz/ctz. Those builtins
|
|
are specified to be undefined at zero, so portable code must check for zero
|
|
and handle it as a special case. That is unnecessary on ARM where those
|
|
operations are implemented in a way that is well-defined for zero. For
|
|
example:
|
|
|
|
int f(int x) { return x ? __builtin_clz(x) : sizeof(int)*8; }
|
|
|
|
should just be implemented with a CLZ instruction. Since there are other
|
|
targets, e.g., PPC, that share this behavior, it would be best to implement
|
|
this in a target-independent way: we should probably fold that (when using
|
|
"undefined at zero" semantics) to set the "defined at zero" bit and have
|
|
the code generator expand out the right code.
|
|
|
|
|
|
//===---------------------------------------------------------------------===//
|
|
|
|
Clean up the test/MC/ARM files to have more robust register choices.
|
|
|
|
R0 should not be used as a register operand in the assembler tests as it's then
|
|
not possible to distinguish between a correct encoding and a missing operand
|
|
encoding, as zero is the default value for the binary encoder.
|
|
e.g.,
|
|
add r0, r0 // bad
|
|
add r3, r5 // good
|
|
|
|
Register operands should be distinct. That is, when the encoding does not
|
|
require two syntactical operands to refer to the same register, two different
|
|
registers should be used in the test so as to catch errors where the
|
|
operands are swapped in the encoding.
|
|
e.g.,
|
|
subs.w r1, r1, r1 // bad
|
|
subs.w r1, r2, r3 // good
|
|
|