75 lines
1.8 KiB
LLVM
75 lines
1.8 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=bdver1 | FileCheck %s
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; Verify that for the architectures that are known to have poor latency
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; double precision shift instructions we generate alternative sequence
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; of instructions with lower latencies instead of shrd instruction.
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;uint64_t rshift1(uint64_t a, uint64_t b)
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;{
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; return (a >> 1) | (b << 63);
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;}
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; CHECK: rshift1:
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; CHECK: shrq {{.*}}
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; CHECK-NEXT: shlq $63, {{.*}}
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; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
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define i64 @rshift1(i64 %a, i64 %b) nounwind readnone uwtable {
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%1 = lshr i64 %a, 1
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%2 = shl i64 %b, 63
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%3 = or i64 %2, %1
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ret i64 %3
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}
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;uint64_t rshift2(uint64_t a, uint64_t b)
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;{
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; return (a >> 2) | (b << 62);
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;}
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; CHECK: rshift2:
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; CHECK: shrq $2, {{.*}}
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; CHECK-NEXT: shlq $62, {{.*}}
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; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
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define i64 @rshift2(i64 %a, i64 %b) nounwind readnone uwtable {
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%1 = lshr i64 %a, 2
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%2 = shl i64 %b, 62
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%3 = or i64 %2, %1
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ret i64 %3
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}
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;uint64_t rshift7(uint64_t a, uint64_t b)
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;{
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; return (a >> 7) | (b << 57);
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;}
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; CHECK: rshift7:
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; CHECK: shrq $7, {{.*}}
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; CHECK-NEXT: shlq $57, {{.*}}
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; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
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define i64 @rshift7(i64 %a, i64 %b) nounwind readnone uwtable {
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%1 = lshr i64 %a, 7
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%2 = shl i64 %b, 57
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%3 = or i64 %2, %1
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ret i64 %3
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}
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;uint64_t rshift63(uint64_t a, uint64_t b)
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;{
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; return (a >> 63) | (b << 1);
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;}
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; CHECK: rshift63:
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; CHECK: shrq $63, {{.*}}
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; CHECK-NEXT: leaq ({{.*}},{{.*}}), {{.*}}
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; CHECK-NEXT: orq {{.*}}, {{.*}}
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define i64 @rshift63(i64 %a, i64 %b) nounwind readnone uwtable {
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%1 = lshr i64 %a, 63
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%2 = shl i64 %b, 1
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%3 = or i64 %2, %1
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ret i64 %3
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}
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