267 lines
9.1 KiB
C++
267 lines
9.1 KiB
C++
//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "Thumb1InstrInfo.h"
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#include "ARM.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/ADT/SmallVector.h"
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#include "Thumb1InstrInfo.h"
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using namespace llvm;
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Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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}
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unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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return 0;
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}
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bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const {
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if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) {
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if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
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return true;
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} else if (SrcRC == ARM::tGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
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return true;
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}
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} else if (DestRC == ARM::tGPRRegisterClass) {
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if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
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return true;
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} else if (SrcRC == ARM::tGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
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return true;
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}
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}
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return false;
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}
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bool Thumb1InstrInfo::
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canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const {
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if (Ops.size() != 1) return false;
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unsigned OpNum = Ops[0];
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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default: break;
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case ARM::tMOVr:
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case ARM::tMOVtgpr2gpr:
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case ARM::tMOVgpr2tgpr:
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case ARM::tMOVgpr2gpr: {
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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!isARMLowRegister(SrcReg))
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// tSpill cannot take a high register operand.
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return false;
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
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!isARMLowRegister(DstReg))
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// tRestore cannot target a high register operand.
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return false;
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}
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return true;
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}
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}
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return false;
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}
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void Thumb1InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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assert((RC == ARM::tGPRRegisterClass ||
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(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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isARMLowRegister(SrcReg))) && "Unknown regclass!");
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if (RC == ARM::tGPRRegisterClass ||
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(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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isARMLowRegister(SrcReg))) {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
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MachineMemOperand::MOStore, 0,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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}
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}
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void Thumb1InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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assert((RC == ARM::tGPRRegisterClass ||
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(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
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isARMLowRegister(DestReg))) && "Unknown regclass!");
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if (RC == ARM::tGPRRegisterClass ||
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(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
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isARMLowRegister(DestReg))) {
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
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MachineMemOperand::MOLoad, 0,
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MFI.getObjectSize(FI),
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MFI.getObjectAlignment(FI));
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
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.addFrameIndex(FI).addImm(0).addMemOperand(MMO));
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}
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}
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bool Thumb1InstrInfo::
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spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
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AddDefaultPred(MIB);
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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bool isKill = true;
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// Add the callee-saved register as live-in unless it's LR and
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// @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress
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// then it's already added to the function and entry block live-in sets.
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if (Reg == ARM::LR) {
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MachineFunction &MF = *MBB.getParent();
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if (MF.getFrameInfo()->isReturnAddressTaken() &&
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MF.getRegInfo().isLiveIn(Reg))
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isKill = false;
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}
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if (isKill) {
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MBB.addLiveIn(Reg);
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MIB.addReg(Reg, RegState::Kill);
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}
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}
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return true;
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}
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bool Thumb1InstrInfo::
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restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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if (CSI.empty())
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return false;
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bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
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DebugLoc DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
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AddDefaultPred(MIB);
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bool NumRegs = false;
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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if (Reg == ARM::LR) {
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// Special epilogue for vararg functions. See emitEpilogue
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if (isVarArg)
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continue;
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Reg = ARM::PC;
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(*MIB).setDesc(get(ARM::tPOP_RET));
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MI = MBB.erase(MI);
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}
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MIB.addReg(Reg, getDefRegState(true));
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NumRegs = true;
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}
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// It's illegal to emit pop instruction without operands.
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if (NumRegs)
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MBB.insert(MI, &*MIB);
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else
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MF.DeleteMachineInstr(MIB);
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return true;
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}
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MachineInstr *Thumb1InstrInfo::
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops, int FI) const {
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if (Ops.size() != 1) return NULL;
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unsigned OpNum = Ops[0];
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unsigned Opc = MI->getOpcode();
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MachineInstr *NewMI = NULL;
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switch (Opc) {
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default: break;
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case ARM::tMOVr:
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case ARM::tMOVtgpr2gpr:
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case ARM::tMOVgpr2tgpr:
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case ARM::tMOVgpr2gpr: {
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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!isARMLowRegister(SrcReg))
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// tSpill cannot take a high register operand.
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break;
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NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0));
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
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!isARMLowRegister(DstReg))
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// tRestore cannot target a high register operand.
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break;
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bool isDead = MI->getOperand(0).isDead();
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NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
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.addReg(DstReg,
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RegState::Define | getDeadRegState(isDead))
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.addFrameIndex(FI).addImm(0));
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}
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break;
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}
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}
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return NewMI;
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}
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