58 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C++
		
	
	
	
			
		
		
	
	
			58 lines
		
	
	
		
			1.9 KiB
		
	
	
	
		
			C++
		
	
	
	
| //===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===//
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| //
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| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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| // See https://llvm.org/LICENSE.txt for license information.
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| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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| //
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| //===----------------------------------------------------------------------===//
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| //
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| // This file contains the entry points for global functions defined in the LLVM
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| // RISC-V back-end.
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| //
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| //===----------------------------------------------------------------------===//
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| 
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| #ifndef LLVM_LIB_TARGET_RISCV_RISCV_H
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| #define LLVM_LIB_TARGET_RISCV_RISCV_H
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| 
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| #include "MCTargetDesc/RISCVBaseInfo.h"
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| #include "llvm/Target/TargetMachine.h"
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| 
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| namespace llvm {
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| class RISCVRegisterBankInfo;
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| class RISCVSubtarget;
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| class RISCVTargetMachine;
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| class AsmPrinter;
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| class FunctionPass;
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| class InstructionSelector;
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| class MCInst;
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| class MCOperand;
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| class MachineInstr;
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| class MachineOperand;
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| class PassRegistry;
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| 
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| void LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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|                                     const AsmPrinter &AP);
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| bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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|                                          MCOperand &MCOp, const AsmPrinter &AP);
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| 
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| FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM);
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| 
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| FunctionPass *createRISCVMergeBaseOffsetOptPass();
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| void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
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| 
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| FunctionPass *createRISCVExpandPseudoPass();
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| void initializeRISCVExpandPseudoPass(PassRegistry &);
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| 
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| FunctionPass *createRISCVExpandAtomicPseudoPass();
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| void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
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| 
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| FunctionPass *createRISCVCleanupVSETVLIPass();
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| void initializeRISCVCleanupVSETVLIPass(PassRegistry &);
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| 
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| InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
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|                                                     RISCVSubtarget &,
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|                                                     RISCVRegisterBankInfo &);
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| }
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| 
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| #endif
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