357 lines
14 KiB
C++
357 lines
14 KiB
C++
//===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that RISCV uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
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#define LLVM_LIB_TARGET_RISCV_RISCVISELLOWERING_H
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#include "RISCV.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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class RISCVSubtarget;
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namespace RISCVISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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RET_FLAG,
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URET_FLAG,
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SRET_FLAG,
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MRET_FLAG,
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CALL,
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/// Select with condition operator - This selects between a true value and
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/// a false value (ops #3 and #4) based on the boolean result of comparing
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/// the lhs and rhs (ops #0 and #1) of a conditional expression with the
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/// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
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/// The lhs and rhs are XLenVT integers. The true and false values can be
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/// integer or floating point.
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SELECT_CC,
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BuildPairF64,
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SplitF64,
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TAIL,
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// RV64I shifts, directly matching the semantics of the named RISC-V
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// instructions.
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SLLW,
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SRAW,
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SRLW,
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// 32-bit operations from RV64M that can't be simply matched with a pattern
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// at instruction selection time. These have undefined behavior for division
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// by 0 or overflow (divw) like their target independent counterparts.
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DIVW,
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DIVUW,
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REMUW,
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// RV64IB rotates, directly matching the semantics of the named RISC-V
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// instructions.
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ROLW,
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RORW,
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// RV64IB funnel shifts, with the semantics of the named RISC-V instructions,
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// but the same operand order as fshl/fshr intrinsics.
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FSRW,
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FSLW,
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// FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as
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// XLEN is the only legal integer width.
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//
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// FMV_H_X matches the semantics of the FMV.H.X.
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// FMV_X_ANYEXTH is similar to FMV.X.H but has an any-extended result.
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// FMV_W_X_RV64 matches the semantics of the FMV.W.X.
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// FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has an any-extended result.
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//
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// This is a more convenient semantic for producing dagcombines that remove
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// unnecessary GPR->FPR->GPR moves.
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FMV_H_X,
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FMV_X_ANYEXTH,
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FMV_W_X_RV64,
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FMV_X_ANYEXTW_RV64,
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// READ_CYCLE_WIDE - A read of the 64-bit cycle CSR on a 32-bit target
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// (returns (Lo, Hi)). It takes a chain operand.
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READ_CYCLE_WIDE,
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// Generalized Reverse and Generalized Or-Combine - directly matching the
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// semantics of the named RISC-V instructions. Lowered as custom nodes as
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// TableGen chokes when faced with commutative permutations in deeply-nested
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// DAGs. Each node takes an input operand and a TargetConstant immediate
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// shift amount, and outputs a bit-manipulated version of input. All operands
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// are of type XLenVT.
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GREVI,
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GREVIW,
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GORCI,
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GORCIW,
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// Vector Extension
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// VMV_X_S matches the semantics of vmv.x.s. The result is always XLenVT
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// sign extended from the vector element size. NOTE: The result size will
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// never be less than the vector element size.
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VMV_X_S,
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// Splats an i64 scalar to a vector type (with element type i64) where the
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// scalar is a sign-extended i32.
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SPLAT_VECTOR_I64,
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// Read VLENB CSR
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READ_VLENB,
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// Truncates a RVV integer vector by one power-of-two.
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TRUNCATE_VECTOR,
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// Unit-stride fault-only-first load
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VLEFF,
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VLEFF_MASK,
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// read vl CSR
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READ_VL,
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// Matches the semantics of vslideup/vslidedown. The first operand is the
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// pass-thru operand, the second is the source vector, and the third is the
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// XLenVT index (either constant or non-constant).
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VSLIDEUP,
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VSLIDEDOWN,
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// Matches the semantics of the unmasked vid.v instruction.
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VID,
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};
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} // namespace RISCVISD
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class RISCVTargetLowering : public TargetLowering {
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const RISCVSubtarget &Subtarget;
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public:
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explicit RISCVTargetLowering(const TargetMachine &TM,
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const RISCVSubtarget &STI);
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const RISCVSubtarget &getSubtarget() const { return Subtarget; }
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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MachineFunction &MF,
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unsigned Intrinsic) const override;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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bool isLegalICmpImmediate(int64_t Imm) const override;
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bool isLegalAddImmediate(int64_t Imm) const override;
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bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
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bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
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bool isCheapToSpeculateCttz() const override;
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bool isCheapToSpeculateCtlz() const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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bool hasBitPreservingFPLogic(EVT VT) const override;
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// Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
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const APInt &DemandedElts,
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TargetLoweringOpt &TLO) const override;
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void computeKnownBitsForTargetNode(const SDValue Op,
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KnownBits &Known,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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// This method returns the name of a target specific DAG node.
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const char *getTargetNodeName(unsigned Opcode) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
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return VT.isScalarInteger();
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}
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bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
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bool shouldInsertFencesForAtomic(const Instruction *I) const override {
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return isa<LoadInst>(I) || isa<StoreInst>(I);
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}
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Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
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AtomicOrdering Ord) const override;
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bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
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EVT VT) const override;
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ISD::NodeType getExtendForAtomicOps() const override {
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return ISD::SIGN_EXTEND;
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}
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ISD::NodeType getExtendForAtomicCmpSwapArg() const override {
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return ISD::SIGN_EXTEND;
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}
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bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
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if (DAG.getMachineFunction().getFunction().hasMinSize())
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return false;
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return true;
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}
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bool isDesirableToCommuteWithShift(const SDNode *N,
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CombineLevel Level) const override;
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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Register
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getExceptionPointerRegister(const Constant *PersonalityFn) const override;
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/// If a physical register, this returns the register that receives the
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/// exception typeid on entry to a landing pad.
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Register
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
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bool shouldExtendTypeInLibCall(EVT Type) const override;
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bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
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/// Returns the register with the specified architectural or ABI name. This
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/// method is necessary to lower the llvm.read_register.* and
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/// llvm.write_register.* intrinsics. Allocatable registers must be reserved
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/// with the clang -ffixed-xX flag for access to be allowed.
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Register getRegisterByName(const char *RegName, LLT VT,
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const MachineFunction &MF) const override;
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// Lower incoming arguments, copy physregs into vregs
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override {
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return true;
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}
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bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
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bool shouldConsiderGEPOffsetSplit() const override { return true; }
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bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
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SDValue C) const override;
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TargetLowering::AtomicExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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Value *emitMaskedAtomicRMWIntrinsic(IRBuilder<> &Builder, AtomicRMWInst *AI,
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Value *AlignedAddr, Value *Incr,
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Value *Mask, Value *ShiftAmt,
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AtomicOrdering Ord) const override;
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TargetLowering::AtomicExpansionKind
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shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
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Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilder<> &Builder,
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AtomicCmpXchgInst *CI,
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Value *AlignedAddr, Value *CmpVal,
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Value *NewVal, Value *Mask,
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AtomicOrdering Ord) const override;
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private:
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void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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bool IsRet) const;
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void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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bool IsRet, CallLoweringInfo *CLI) const;
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template <class NodeTy>
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SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
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SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
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bool UseGOT) const;
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SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
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SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
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SDValue lowerSPLATVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVectorMaskExt(SDValue Op, SelectionDAG &DAG,
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int64_t ExtTrueVal) const;
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SDValue lowerVectorMaskTrunc(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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bool isEligibleForTailCallOptimization(
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CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
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const SmallVector<CCValAssign, 16> &ArgLocs) const;
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/// Generate error diagnostics if any register used by CC has been marked
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/// reserved.
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void validateCCReservedRegs(
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const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs,
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MachineFunction &MF) const;
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};
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namespace RISCVVIntrinsicsTable {
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struct RISCVVIntrinsicInfo {
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unsigned int IntrinsicID;
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unsigned int ExtendedOperand;
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};
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using namespace RISCV;
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#define GET_RISCVVIntrinsicsTable_DECL
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#include "RISCVGenSearchableTables.inc"
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} // end namespace RISCVVIntrinsicsTable
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namespace RISCVZvlssegTable {
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struct RISCVZvlsseg {
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unsigned int IntrinsicID;
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unsigned int SEW;
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unsigned int LMUL;
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unsigned int IndexLMUL;
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unsigned int Pseudo;
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};
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using namespace RISCV;
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#define GET_RISCVZvlssegTable_DECL
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#include "RISCVGenSearchableTables.inc"
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} // namespace RISCVZvlssegTable
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}
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#endif
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