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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 75620fadf5 [RISCV] Change how we encode AVL operands in vector pseudoinstructions to use GPRNoX0. 
This patch changes the register class to avoid accidentally setting
the AVL operand to X0 through MachineIR optimizations.

There are cases where we really want to use X0, but we can't get that
past the MachineVerifier with the register class as GPRNoX0. So I've
use a 64-bit -1 as a sentinel for X0. All other immediate values should
be uimm5. I convert it to X0 at the earliest possible point in the VSETVLI
insertion pass to avoid touching the rest of the algorithm. In
SelectionDAG lowering I'm using a -1 TargetConstant to hide it from
instruction selection and treat it differently than if the user
used -1. A user -1 should be selected to a register since it doesn't
fit in uimm5.

This is the rest of the changes started in D109110. As mentioned there,
I don't have a failing test from MachineIR optimizations anymore.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D109116
 		2021-09-03 09:19:25 -07:00
..
AsmParser [RISCV] Use ~0ULL instead of ~0U when checking for invalid ErrorInfo. 2021-08-27 12:30:33 -07:00
Disassembler
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MCTargetDesc Fix typo in RISCVMatInt.cpp comments 2021-09-02 18:11:09 -07:00
TargetInfo
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CMakeLists.txt [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks. 2021-05-24 11:47:27 -07:00
RISCV.h [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks. 2021-05-24 11:47:27 -07:00
RISCV.td [RISCV] Add SiFive core S51 2021-09-02 18:45:25 -07:00
RISCVAsmPrinter.cpp [RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter. 2021-05-10 09:33:23 +08:00
RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp [RISCV] Split PseudoVSETVLI into 2 instructions to allow different register classes for rs1. 2021-09-02 07:45:31 -07:00
RISCVFrameLowering.cpp [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
RISCVFrameLowering.h [RISCV] Enable shrink wrap by default 2021-09-02 09:47:58 -05:00
RISCVISelDAGToDAG.cpp [RISCV] Teach instruction selection to elide sext.w in some cases. 2021-09-02 07:54:34 -07:00
RISCVISelDAGToDAG.h [RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns. 2021-08-18 11:07:11 -07:00
RISCVISelLowering.cpp [RISCV] Change how we encode AVL operands in vector pseudoinstructions to use GPRNoX0. 2021-09-03 09:19:25 -07:00
RISCVISelLowering.h [DAGCombiner] Add target hook function to decide folding (mul (add x, c1), c2) 2021-08-22 16:53:32 +08:00
RISCVInsertVSETVLI.cpp [RISCV] Change how we encode AVL operands in vector pseudoinstructions to use GPRNoX0. 2021-09-03 09:19:25 -07:00
RISCVInstrFormats.td [RISCV] Move the $rs operand of PseudoStore from outs to ins. NFC 2021-08-08 15:58:24 -07:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp [RISCV] Fix reporting of incorrect commutable operand indices 2021-08-20 10:27:15 +01:00
RISCVInstrInfo.h [RISCV] Change how we encode AVL operands in vector pseudoinstructions to use GPRNoX0. 2021-09-03 09:19:25 -07:00
RISCVInstrInfo.td [RISCV] Teach instruction selection to elide sext.w in some cases. 2021-09-02 07:54:34 -07:00
RISCVInstrInfoA.td [RISCV][NFC] Add explicit type i64 to RV64 only patterns. 2021-04-09 09:37:04 +08:00
RISCVInstrInfoB.td [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64. 2021-08-26 10:20:19 -07:00
RISCVInstrInfoC.td [RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg. 2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td [RISCV] Support FP_TO_S/UINT_SAT for i32 and i64. 2021-08-07 16:06:00 -07:00
RISCVInstrInfoF.td [RISCV] Support FP_TO_S/UINT_SAT for i32 and i64. 2021-08-07 16:06:00 -07:00
RISCVInstrInfoM.td [RISCV] Remove sext_inreg+add/sub/mul/shl isel patterns. 2021-08-18 11:07:11 -07:00
RISCVInstrInfoV.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVInstrInfoVPseudos.td [RISCV] Change how we encode AVL operands in vector pseudoinstructions to use GPRNoX0. 2021-09-03 09:19:25 -07:00
RISCVInstrInfoVSDPatterns.td [RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions. 2021-08-04 10:39:50 -07:00
RISCVInstrInfoVVLPatterns.td [RISCV] Improve codegen for shuffles with LHS/RHS splats 2021-08-09 10:31:40 +01:00
RISCVInstrInfoZfh.td [RISCV] Support FP_TO_S/UINT_SAT for i32 and i64. 2021-08-07 16:06:00 -07:00
RISCVInstructionSelector.cpp
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RISCVLegalizerInfo.cpp [globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one 2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp [RISCV] Remove the _COMMUTABLE and _TA versions of FMA and wide FMA vector instructions. 2021-08-04 10:39:50 -07:00
RISCVMachineFunctionInfo.h [RISCV] Don't emit save-restore call if function is a interrupt handler 2021-04-16 12:54:47 +08:00
RISCVMergeBaseOffset.cpp [RISCV] Indicate that RISCVMergeBaseOffsetOpt preserves the CFG. 2021-08-03 08:32:36 -07:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp [RISCV] Reserve an emergency spill slot for any RVV spills 2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
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RISCVRegisterInfo.td [RISCV] Make VLEN no greater than 65536 2021-07-17 12:47:46 +08:00
RISCVSchedRocket.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVSchedSiFive7.td [RISCV] Fix typo in RISCVSchedSiFive7.td 2021-09-01 16:39:48 -05:00
RISCVSchedule.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVScheduleB.td [RISCV] Move scheduling resources for B into a separate file (NFC) 2021-03-29 20:37:22 -05:00
RISCVScheduleV.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVSubtarget.cpp [RISCV] Add -riscv-v-fixed-length-vector-elen-max to limit the ELEN used for fixed length vectorization. 2021-08-27 10:17:35 -07:00
RISCVSubtarget.h [RISCV] Add -riscv-v-fixed-length-vector-elen-max to limit the ELEN used for fixed length vectorization. 2021-08-27 10:17:35 -07:00
RISCVSystemOperands.td RISCV: add a few deprecated aliases for CSRs 2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp [RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks. 2021-05-24 11:47:27 -07:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp [RISCV] Add zext.h/zext.w to RISCVTTIImpl::getIntImmCostInst. 2021-08-18 09:40:40 -07:00
RISCVTargetTransformInfo.h [SLP][RISCV] Implement unsigned getMinVectorRegisterBitWidth() for RISCV 2021-09-01 14:25:15 +08:00