David Sherwood 57ca65e21e [AArch64] Add instruction costs for FP_TO_UINT and FP_TO_SINT with half types ... We were missing some instruction costs when converting vectors of floating point half types into integers, so I've added those here. I also manually generated assembly code for each FP->int case and looked at the number of instructions generated, which meant adjusting some of the existing costs too. I've updated an existing test to reflect the new costs: Analysis/CostModel/AArch64/sve-fptoi.ll Differential Revision: https://reviews.llvm.org/D99935		2021-04-21 09:39:45 +01:00
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AArch64	[AArch64] Add instruction costs for FP_TO_UINT and FP_TO_SINT with half types	2021-04-21 09:39:45 +01:00
AMDGPU	[AMDGPU][CostModel] Refine cost model for control-flow instructions.	2021-04-10 09:20:24 +03:00
ARM	[InstructionCost] Don't conflate Invalid costs with Unknown costs.	2021-03-30 09:29:42 +01:00
PowerPC	[Cost]Canonicalize the cost for logical or/and reductions.	2021-03-19 11:01:58 -07:00
RISCV	[RISCV] Reorder checks in RISCVTTIImpl::getGatherScatterOpCost to avoid calling getMinRVVVectorSizeInBits() when V extension is not enabled.	2021-03-25 14:20:47 -07:00
SystemZ	[Cost]Canonicalize the cost for logical or/and reductions.	2021-03-19 11:01:58 -07:00
X86	[X86][CostModel] X86TTIImpl::getShuffleCost(): subvector insertions are cheap	2021-04-19 13:24:58 +03:00
free-intrinsics-datalayout.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
free-intrinsics-no_info.ll	[noalias.decl] Look through llvm.experimental.noalias.scope.decl	2021-01-19 20:09:42 +01:00
no_info.ll	…