llvm-project/llvm/test/CodeGen
Craig Topper 78abad569c [RISCV] Add missing SEW=64 tests to vmslt-rv32.ll. NFC 2021-04-20 18:31:36 -07:00
..
AArch64 Make sure PHIElimination doesn't copy debug locations across basic blocks. 2021-04-20 17:03:29 -07:00
AMDGPU [AMDGPU] Allow multiple uses of the same literal 2021-04-20 16:44:01 +01:00
ARC
ARM [ARM] Limit PerformExtractEltToVMOVRRD to when f64 is legal. 2021-04-20 16:24:36 +01:00
AVR
BPF BPF: remove default .extern data section 2021-04-13 11:35:52 -07:00
Generic Restore lit feature object-emission. Omit DebugInfo/Generic on XCore. 2021-04-16 13:02:14 +01:00
Hexagon [Hexagon] Avoid infinite loops in type legalization when lowering SETCC 2021-04-15 13:34:37 -05:00
Inputs
Lanai
M68k [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling 2021-03-19 16:02:31 +00:00
MIR [AMDGPU] Set implicit arg attributes for indirect calls 2021-04-13 13:15:13 +00:00
MSP430
Mips [MIPS, test] Fix use of undef FileCheck var 2021-04-02 00:59:49 +01:00
NVPTX [NVPTX] Handle bitcast and ASC(101) when trying to avoid argument copy. 2021-04-06 13:06:00 -07:00
PowerPC [PowerPC] Canonicalize shuffles on big endian targets as well 2021-04-20 07:29:47 -05:00
RISCV [RISCV] Add missing SEW=64 tests to vmslt-rv32.ll. NFC 2021-04-20 18:31:36 -07:00
SPARC
SystemZ
Thumb Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
Thumb2 [ARM] Create VMOVRRD from adjacent vector extracts 2021-04-20 15:15:43 +01:00
VE
WebAssembly [WebAssembly] More codegen for f64x2.convert_low_i32x4_{s,u} 2021-04-20 12:37:13 -07:00
WinCFGuard
WinEH
X86 [X86][SSE] combineX86ShuffleChain - check if we're blending with zero into already zero elements 2021-04-20 17:09:49 +01:00
XCore [CodeGen] Report a normal instead of fatal error for label redefinition 2021-03-09 10:54:41 +00:00