llvm-project/llvm/test/tools/llvm-mca/ARM
David Penry 78a871abf7 [ARM] Use ProcResGroup in Cortex-M7 scheduling model
Used to model structural hazards on FP issue, where some
instructions take up 2 issue slots and others one as well
as similar structural hazards on load issue, where some
instructions take up two load lanes and others one.

Differential Revision: https://reviews.llvm.org/D98977
2021-04-19 21:23:05 +01:00
..
cortex-a57-basic-instructions.s Add support for branch forms of ALU instructions to Cortex-A57 model 2020-11-24 11:43:51 +03:00
cortex-a57-memory-instructions.s [ARM][SchedModels] Convert IsLdstsoScaledNotOptimalPred to MCSchedPredicate 2020-10-26 20:22:41 +03:00
cortex-a57-neon-instructions.s [llvm-mca] Add test for cortex-a57 NEON instructions 2020-10-23 10:55:54 +03:00
cortex-a57-thumb.s [llvm-mca] Fix processing thumb instruction set 2020-11-24 18:27:59 +03:00
lit.local.cfg
m4-int.s [ARM] Removed hasSideEffects from signed/unsigned saturates 2020-10-01 14:55:01 +00:00
m4-targetfeatures.s
m7-fp.s [ARM] Use ProcResGroup in Cortex-M7 scheduling model 2021-04-19 21:23:05 +01:00
m7-int.s [ARM] Use ProcResGroup in Cortex-M7 scheduling model 2021-04-19 21:23:05 +01:00
m7-negative-readadvance.s [ARM] Use ProcResGroup in Cortex-M7 scheduling model 2021-04-19 21:23:05 +01:00
memcpy-ldm-stm.s
simple-cortex-m33.s
simple-test-cortex-a9.s
unsupported-write-variant.s
vld1-index-update.s