llvm-project/llvm/test/tools/llvm-mca/X86
Andrea Di Biagio f5bdc88e4d [MCA] Improved handling of negative read-advance cycles.
Before this patch, register writes were always invalidated by the
RegisterFile at instruction commit stage. So,
the RegisterFile was often losing the knowledge about the `execute
cycle` of writes already committed. While this was not problematic
for non-delayed reads, this was sometimes leading to inaccurate read
latency computations in the presence of negative read-advance cycles.

This patch fixes the issue by changing how the RegisterFile component
internally keeps track of the `execute cycle` information of each
write. On every instruction executed, the RegisterFile gets notified
by the RetireStage, so that it can internally record the execute
cycle of each executed write.
The `execute cycle` information is stored within WriteRef itself, and
it is not invalidated when the write is committed.
2021-03-23 14:47:23 +00:00
..
Atom [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
Barcelona [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
BdVer2 [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
Broadwell [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
BtVer2 [MCA] Improved handling of negative read-advance cycles. 2021-03-23 14:47:23 +00:00
Generic [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
Haswell [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
SLM [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
SandyBridge [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
SkylakeClient [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
SkylakeServer [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
Znver1 [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
Znver2 [TableGen][ARM][X86] Detect combining IntrReadMem and IntrWriteMem. 2020-12-19 14:56:17 -08:00
bextr-read-after-ld.s
bzhi-read-after-ld.s
cpus.s
default-iterations.s
dispatch_width.s
fma3-read-after-ld-1.s
fma3-read-after-ld-2.s
in-order-cpu.s [MCA] Add support for in-order CPUs 2021-03-04 14:08:19 +03:00
intel-syntax.s
invalid-assembly-sequence.s
invalid-cpu.s
invalid-empty-file.s
lit.local.cfg
llvm-mca-markers-1.s
llvm-mca-markers-2.s
llvm-mca-markers-3.s
llvm-mca-markers-4.s
llvm-mca-markers-5.s
llvm-mca-markers-6.s
llvm-mca-markers-7.s
llvm-mca-markers-8.s
llvm-mca-markers-9.s
llvm-mca-markers-10.s
llvm-mca-markers-11.s
llvm-mca-markers-12.s
no-sched-model.s
option-all-stats-1.s
option-all-stats-2.s
option-all-views-1.s
option-all-views-2.s
option-no-stats-1.s
print-imm-hex-1.s
print-imm-hex-2.s
read-after-ld-1.s
read-after-ld-2.s
read-after-ld-3.s
register-file-statistics.s
scheduler-queue-usage.s
show-encoding.s
sqrt-rsqrt-rcp-memop.s
uop-queue.s
variable-blend-read-after-ld-1.s
variable-blend-read-after-ld-2.s