405 lines
9.7 KiB
C
405 lines
9.7 KiB
C
// RUN: %clang_cc1 -ffreestanding -triple armv8-eabi -target-cpu cortex-a57 -O -S -emit-llvm -o - %s | FileCheck %s -check-prefix=ARM -check-prefix=AArch32
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// RUN: %clang_cc1 -ffreestanding -triple aarch64-eabi -target-cpu cortex-a57 -target-feature +neon -target-feature +crc -target-feature +crypto -O -S -emit-llvm -o - %s | FileCheck %s -check-prefix=ARM -check-prefix=AArch64
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#include <arm_acle.h>
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/* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */
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/* 8.3 Memory Barriers */
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// ARM-LABEL: test_dmb
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// AArch32: call void @llvm.arm.dmb(i32 1)
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// AArch64: call void @llvm.aarch64.dmb(i32 1)
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void test_dmb(void) {
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__dmb(1);
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}
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// ARM-LABEL: test_dsb
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// AArch32: call void @llvm.arm.dsb(i32 2)
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// AArch64: call void @llvm.aarch64.dsb(i32 2)
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void test_dsb(void) {
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__dsb(2);
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}
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// ARM-LABEL: test_isb
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// AArch32: call void @llvm.arm.isb(i32 3)
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// AArch64: call void @llvm.aarch64.isb(i32 3)
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void test_isb(void) {
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__isb(3);
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}
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/* 8.4 Hints */
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// ARM-LABEL: test_yield
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// AArch32: call void @llvm.arm.hint(i32 1)
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// AArch64: call void @llvm.aarch64.hint(i32 1)
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void test_yield(void) {
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__yield();
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}
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// ARM-LABEL: test_wfe
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// AArch32: call void @llvm.arm.hint(i32 2)
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// AArch64: call void @llvm.aarch64.hint(i32 2)
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void test_wfe(void) {
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__wfe();
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}
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// ARM-LABEL: test_wfi
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// AArch32: call void @llvm.arm.hint(i32 3)
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// AArch64: call void @llvm.aarch64.hint(i32 3)
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void test_wfi(void) {
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__wfi();
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}
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// ARM-LABEL: test_sev
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// AArch32: call void @llvm.arm.hint(i32 4)
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// AArch64: call void @llvm.aarch64.hint(i32 4)
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void test_sev(void) {
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__sev();
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}
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// ARM-LABEL: test_sevl
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// AArch32: call void @llvm.arm.hint(i32 5)
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// AArch64: call void @llvm.aarch64.hint(i32 5)
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void test_sevl(void) {
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__sevl();
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}
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#if __ARM_32BIT_STATE
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// AArch32-LABEL: test_dbg
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// AArch32: call void @llvm.arm.dbg(i32 0)
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void test_dbg(void) {
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__dbg(0);
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}
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#endif
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/* 8.5 Swap */
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// ARM-LABEL: test_swp
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// AArch32: call i32 @llvm.arm.ldrex
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// AArch32: call i32 @llvm.arm.strex
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// AArch64: call i64 @llvm.aarch64.ldxr
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// AArch64: call i32 @llvm.aarch64.stxr
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uint32_t test_swp(uint32_t x, volatile void *p) {
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__swp(x, p);
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}
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/* 8.6 Memory prefetch intrinsics */
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/* 8.6.1 Data prefetch */
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// ARM-LABEL: test_pld
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// ARM: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 1)
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void test_pld() {
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__pld(0);
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}
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// ARM-LABEL: test_pldx
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// AArch32: call void @llvm.prefetch(i8* null, i32 1, i32 3, i32 1)
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// AArch64: call void @llvm.prefetch(i8* null, i32 1, i32 1, i32 1)
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void test_pldx() {
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__pldx(1, 2, 0, 0);
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}
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/* 8.6.2 Instruction prefetch */
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// ARM-LABEL: test_pli
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// ARM: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 0)
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void test_pli() {
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__pli(0);
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}
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// ARM-LABEL: test_plix
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// AArch32: call void @llvm.prefetch(i8* null, i32 0, i32 3, i32 0)
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// AArch64: call void @llvm.prefetch(i8* null, i32 0, i32 1, i32 0)
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void test_plix() {
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__plix(2, 0, 0);
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}
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/* 8.7 NOP */
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// ARM-LABEL: test_nop
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// AArch32: call void @llvm.arm.hint(i32 0)
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// AArch64: call void @llvm.aarch64.hint(i32 0)
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void test_nop(void) {
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__nop();
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}
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/* 9 DATA-PROCESSING INTRINSICS */
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/* 9.2 Miscellaneous data-processing intrinsics */
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// ARM-LABEL: test_ror
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// ARM: lshr
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// ARM: sub
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// ARM: shl
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// ARM: or
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uint32_t test_ror(uint32_t x, uint32_t y) {
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return __ror(x, y);
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}
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// ARM-LABEL: test_rorl
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// ARM: lshr
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// ARM: sub
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// ARM: shl
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// ARM: or
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unsigned long test_rorl(unsigned long x, uint32_t y) {
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return __rorl(x, y);
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}
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// ARM-LABEL: test_rorll
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// ARM: lshr
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// ARM: sub
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// ARM: shl
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// ARM: or
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uint64_t test_rorll(uint64_t x, uint32_t y) {
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return __rorll(x, y);
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}
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// ARM-LABEL: test_clz
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// ARM: call i32 @llvm.ctlz.i32(i32 %t, i1 false)
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uint32_t test_clz(uint32_t t) {
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return __clz(t);
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}
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// ARM-LABEL: test_clzl
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// AArch32: call i32 @llvm.ctlz.i32(i32 %t, i1 false)
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// AArch64: call i64 @llvm.ctlz.i64(i64 %t, i1 false)
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long test_clzl(long t) {
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return __clzl(t);
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}
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// ARM-LABEL: test_clzll
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// ARM: call i64 @llvm.ctlz.i64(i64 %t, i1 false)
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uint64_t test_clzll(uint64_t t) {
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return __clzll(t);
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}
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// ARM-LABEL: test_rev
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// ARM: call i32 @llvm.bswap.i32(i32 %t)
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uint32_t test_rev(uint32_t t) {
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return __rev(t);
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}
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// ARM-LABEL: test_revl
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// AArch32: call i32 @llvm.bswap.i32(i32 %t)
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// AArch64: call i64 @llvm.bswap.i64(i64 %t)
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long test_revl(long t) {
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return __revl(t);
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}
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// ARM-LABEL: test_revll
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// ARM: call i64 @llvm.bswap.i64(i64 %t)
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uint64_t test_revll(uint64_t t) {
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return __revll(t);
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}
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// ARM-LABEL: test_rev16
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// ARM: llvm.bswap
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// ARM: lshr
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// ARM: shl
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// ARM: or
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uint32_t test_rev16(uint32_t t) {
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return __rev16(t);
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}
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// ARM-LABEL: test_rev16l
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// ARM: llvm.bswap
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// ARM: lshr
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// ARM: shl
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// ARM: or
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long test_rev16l(long t) {
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return __rev16l(t);
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}
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// ARM-LABEL: test_rev16ll
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// ARM: llvm.bswap
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// ARM: lshr
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// ARM: shl
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// ARM: or
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uint64_t test_rev16ll(uint64_t t) {
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return __rev16ll(t);
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}
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// ARM-LABEL: test_revsh
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// ARM: call i16 @llvm.bswap.i16(i16 %t)
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int16_t test_revsh(int16_t t) {
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return __revsh(t);
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}
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// ARM-LABEL: test_rbit
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// AArch32: call i32 @llvm.arm.rbit
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// AArch64: call i32 @llvm.aarch64.rbit.i32
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uint32_t test_rbit(uint32_t t) {
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return __rbit(t);
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}
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// ARM-LABEL: test_rbitl
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// AArch32: call i32 @llvm.arm.rbit
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// AArch64: call i64 @llvm.aarch64.rbit.i64
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long test_rbitl(long t) {
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return __rbitl(t);
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}
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// ARM-LABEL: test_rbitll
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// AArch32: call i32 @llvm.arm.rbit
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// AArch32: call i32 @llvm.arm.rbit
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// AArch64: call i64 @llvm.aarch64.rbit.i64
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uint64_t test_rbitll(uint64_t t) {
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return __rbitll(t);
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}
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/* 9.4 Saturating intrinsics */
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#ifdef __ARM_32BIT_STATE
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/* 9.4.1 Width-specified saturation intrinsics */
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// AArch32-LABEL: test_ssat
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// AArch32: call i32 @llvm.arm.ssat(i32 %t, i32 1)
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int32_t test_ssat(int32_t t) {
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return __ssat(t, 1);
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}
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// AArch32-LABEL: test_usat
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// AArch32: call i32 @llvm.arm.usat(i32 %t, i32 2)
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int32_t test_usat(int32_t t) {
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return __usat(t, 2);
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}
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/* 9.4.2 Saturating addition and subtraction intrinsics */
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// AArch32-LABEL: test_qadd
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// AArch32: call i32 @llvm.arm.qadd(i32 %a, i32 %b)
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int32_t test_qadd(int32_t a, int32_t b) {
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return __qadd(a, b);
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}
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// AArch32-LABEL: test_qsub
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// AArch32: call i32 @llvm.arm.qsub(i32 %a, i32 %b)
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int32_t test_qsub(int32_t a, int32_t b) {
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return __qsub(a, b);
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}
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extern int32_t f();
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// AArch32-LABEL: test_qdbl
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// AArch32: [[VAR:%[a-z0-9]+]] = {{.*}} call {{.*}} @f
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// AArch32-NOT: call {{.*}} @f
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// AArch32: call i32 @llvm.arm.qadd(i32 [[VAR]], i32 [[VAR]])
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int32_t test_qdbl() {
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return __qdbl(f());
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}
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#endif
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/* 9.7 CRC32 intrinsics */
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// ARM-LABEL: test_crc32b
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// AArch32: call i32 @llvm.arm.crc32b
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// AArch64: call i32 @llvm.aarch64.crc32b
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uint32_t test_crc32b(uint32_t a, uint8_t b) {
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return __crc32b(a, b);
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}
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// ARM-LABEL: test_crc32h
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// AArch32: call i32 @llvm.arm.crc32h
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// AArch64: call i32 @llvm.aarch64.crc32h
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uint32_t test_crc32h(uint32_t a, uint16_t b) {
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return __crc32h(a, b);
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}
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// ARM-LABEL: test_crc32w
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// AArch32: call i32 @llvm.arm.crc32w
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// AArch64: call i32 @llvm.aarch64.crc32w
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uint32_t test_crc32w(uint32_t a, uint32_t b) {
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return __crc32w(a, b);
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}
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// ARM-LABEL: test_crc32d
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// AArch32: call i32 @llvm.arm.crc32w
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// AArch32: call i32 @llvm.arm.crc32w
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// AArch64: call i32 @llvm.aarch64.crc32x
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uint32_t test_crc32d(uint32_t a, uint64_t b) {
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return __crc32d(a, b);
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}
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// ARM-LABEL: test_crc32cb
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// AArch32: call i32 @llvm.arm.crc32cb
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// AArch64: call i32 @llvm.aarch64.crc32cb
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uint32_t test_crc32cb(uint32_t a, uint8_t b) {
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return __crc32cb(a, b);
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}
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// ARM-LABEL: test_crc32ch
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// AArch32: call i32 @llvm.arm.crc32ch
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// AArch64: call i32 @llvm.aarch64.crc32ch
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uint32_t test_crc32ch(uint32_t a, uint16_t b) {
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return __crc32ch(a, b);
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}
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// ARM-LABEL: test_crc32cw
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// AArch32: call i32 @llvm.arm.crc32cw
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// AArch64: call i32 @llvm.aarch64.crc32cw
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uint32_t test_crc32cw(uint32_t a, uint32_t b) {
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return __crc32cw(a, b);
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}
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// ARM-LABEL: test_crc32cd
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// AArch32: call i32 @llvm.arm.crc32cw
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// AArch32: call i32 @llvm.arm.crc32cw
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// AArch64: call i32 @llvm.aarch64.crc32cx
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uint32_t test_crc32cd(uint32_t a, uint64_t b) {
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return __crc32cd(a, b);
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}
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/* 10.1 Special register intrinsics */
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// ARM-LABEL: test_rsr
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// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
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// AArch32: call i32 @llvm.read_register.i32(metadata ![[M2:[0-9]]])
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uint32_t test_rsr() {
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#ifdef __ARM_32BIT_STATE
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return __arm_rsr("cp1:2:c3:c4:5");
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#else
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return __arm_rsr("1:2:3:4:5");
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#endif
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}
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// ARM-LABEL: test_rsr64
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// AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
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// AArch32: call i64 @llvm.read_register.i64(metadata ![[M3:[0-9]]])
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uint64_t test_rsr64() {
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#ifdef __ARM_32BIT_STATE
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return __arm_rsr64("cp1:2:c3");
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#else
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return __arm_rsr64("1:2:3:4:5");
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#endif
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}
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// ARM-LABEL: test_rsrp
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// AArch64: call i64 @llvm.read_register.i64(metadata ![[M1:[0-9]]])
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// AArch32: call i32 @llvm.read_register.i32(metadata ![[M4:[0-9]]])
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void *test_rsrp() {
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return __arm_rsrp("sysreg");
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}
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// ARM-LABEL: test_wsr
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// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}})
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// AArch32: call void @llvm.write_register.i32(metadata ![[M2:[0-9]]], i32 %{{.*}})
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void test_wsr(uint32_t v) {
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#ifdef __ARM_32BIT_STATE
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__arm_wsr("cp1:2:c3:c4:5", v);
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#else
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__arm_wsr("1:2:3:4:5", v);
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#endif
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}
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// ARM-LABEL: test_wsr64
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// AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}})
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// AArch32: call void @llvm.write_register.i64(metadata ![[M3:[0-9]]], i64 %{{.*}})
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void test_wsr64(uint64_t v) {
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#ifdef __ARM_32BIT_STATE
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__arm_wsr64("cp1:2:c3", v);
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#else
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__arm_wsr64("1:2:3:4:5", v);
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#endif
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}
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// ARM-LABEL: test_wsrp
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// AArch64: call void @llvm.write_register.i64(metadata ![[M1:[0-9]]], i64 %{{.*}})
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// AArch32: call void @llvm.write_register.i32(metadata ![[M4:[0-9]]], i32 %{{.*}})
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void test_wsrp(void *v) {
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__arm_wsrp("sysreg", v);
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}
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// AArch32: ![[M2]] = !{!"cp1:2:c3:c4:5"}
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// AArch32: ![[M3]] = !{!"cp1:2:c3"}
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// AArch32: ![[M4]] = !{!"sysreg"}
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// AArch64: ![[M0]] = !{!"1:2:3:4:5"}
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// AArch64: ![[M1]] = !{!"sysreg"}
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