187 lines
4.2 KiB
ArmAsm
187 lines
4.2 KiB
ArmAsm
//===-- save.S - save up to 12 callee-saved registers ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Multiple entry points depending on number of registers to save
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//
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//===----------------------------------------------------------------------===//
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// The entry points are grouped up into 2s for rv64 and 4s for rv32 since this
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// is the minimum grouping which will maintain the required 16-byte stack
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// alignment.
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.text
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#if __riscv_xlen == 32
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.globl __riscv_save_12
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.type __riscv_save_12,@function
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__riscv_save_12:
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addi sp, sp, -64
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mv t1, zero
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sw s11, 12(sp)
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j .Lriscv_save_11_8
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.globl __riscv_save_11
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.type __riscv_save_11,@function
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.globl __riscv_save_10
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.type __riscv_save_10,@function
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.globl __riscv_save_9
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.type __riscv_save_9,@function
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.globl __riscv_save_8
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.type __riscv_save_8,@function
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__riscv_save_11:
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__riscv_save_10:
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__riscv_save_9:
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__riscv_save_8:
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addi sp, sp, -64
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li t1, 16
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.Lriscv_save_11_8:
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sw s10, 16(sp)
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sw s9, 20(sp)
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sw s8, 24(sp)
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sw s7, 28(sp)
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j .Lriscv_save_7_4
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.globl __riscv_save_7
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.type __riscv_save_7,@function
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.globl __riscv_save_6
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.type __riscv_save_6,@function
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.globl __riscv_save_5
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.type __riscv_save_5,@function
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.globl __riscv_save_4
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.type __riscv_save_4,@function
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__riscv_save_7:
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__riscv_save_6:
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__riscv_save_5:
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__riscv_save_4:
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addi sp, sp, -64
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li t1, 32
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.Lriscv_save_7_4:
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sw s6, 32(sp)
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sw s5, 36(sp)
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sw s4, 40(sp)
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sw s3, 44(sp)
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sw s2, 48(sp)
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sw s1, 52(sp)
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sw s0, 56(sp)
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sw ra, 60(sp)
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add sp, sp, t1
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jr t0
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.globl __riscv_save_3
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.type __riscv_save_3,@function
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.globl __riscv_save_2
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.type __riscv_save_2,@function
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.globl __riscv_save_1
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.type __riscv_save_1,@function
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.globl __riscv_save_0
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.type __riscv_save_0,@function
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__riscv_save_3:
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__riscv_save_2:
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__riscv_save_1:
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__riscv_save_0:
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addi sp, sp, -16
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sw s2, 0(sp)
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sw s1, 4(sp)
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sw s0, 8(sp)
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sw ra, 12(sp)
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jr t0
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#elif __riscv_xlen == 64
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.globl __riscv_save_12
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.type __riscv_save_12,@function
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__riscv_save_12:
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addi sp, sp, -112
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mv t1, zero
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sd s11, 8(sp)
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j .Lriscv_save_11_10
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.globl __riscv_save_11
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.type __riscv_save_11,@function
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.globl __riscv_save_10
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.type __riscv_save_10,@function
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__riscv_save_11:
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__riscv_save_10:
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addi sp, sp, -112
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li t1, 16
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.Lriscv_save_11_10:
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sd s10, 16(sp)
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sd s9, 24(sp)
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j .Lriscv_save_9_8
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.globl __riscv_save_9
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.type __riscv_save_9,@function
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.globl __riscv_save_8
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.type __riscv_save_8,@function
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__riscv_save_9:
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__riscv_save_8:
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addi sp, sp, -112
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li t1, 32
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.Lriscv_save_9_8:
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sd s8, 32(sp)
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sd s7, 40(sp)
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j .Lriscv_save_7_6
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.globl __riscv_save_7
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.type __riscv_save_7,@function
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.globl __riscv_save_6
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.type __riscv_save_6,@function
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__riscv_save_7:
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__riscv_save_6:
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addi sp, sp, -112
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li t1, 48
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.Lriscv_save_7_6:
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sd s6, 48(sp)
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sd s5, 56(sp)
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j .Lriscv_save_5_4
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.globl __riscv_save_5
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.type __riscv_save_5,@function
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.globl __riscv_save_4
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.type __riscv_save_4,@function
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__riscv_save_5:
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__riscv_save_4:
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addi sp, sp, -112
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li t1, 64
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.Lriscv_save_5_4:
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sd s4, 64(sp)
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sd s3, 72(sp)
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j .Lriscv_save_3_2
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.globl __riscv_save_3
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.type __riscv_save_3,@function
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.globl __riscv_save_2
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.type __riscv_save_2,@function
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__riscv_save_3:
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__riscv_save_2:
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addi sp, sp, -112
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li t1, 80
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.Lriscv_save_3_2:
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sd s2, 80(sp)
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sd s1, 88(sp)
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sd s0, 96(sp)
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sd ra, 104(sp)
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add sp, sp, t1
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jr t0
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.globl __riscv_save_1
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.type __riscv_save_1,@function
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.globl __riscv_save_0
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.type __riscv_save_0,@function
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__riscv_save_1:
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__riscv_save_0:
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addi sp, sp, -16
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sd s0, 0(sp)
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sd ra, 8(sp)
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jr t0
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#else
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# error "xlen must be 32 or 64 for save-restore implementation
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#endif
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