209 lines
6.2 KiB
LLVM
209 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine -S < %s | FileCheck %s
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; PR5438
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define i32 @test1(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP1]], -1
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; CHECK-NEXT: [[DOTLOBIT_NOT:%.*]] = lshr i32 [[TMP2]], 31
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; CHECK-NEXT: ret i32 [[DOTLOBIT_NOT]]
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;
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%t0 = icmp sgt i32 %a, -1
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%t1 = icmp slt i32 %b, 0
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%t2 = xor i1 %t1, %t0
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%t3 = zext i1 %t2 to i32
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ret i32 %t3
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}
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; TODO: This optimizes partially but not all the way.
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define i32 @test2(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], 3
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; CHECK-NEXT: [[DOTLOBIT:%.*]] = and i32 [[TMP2]], 1
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; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[DOTLOBIT]], 1
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; CHECK-NEXT: ret i32 [[TMP3]]
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;
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%t0 = and i32 %a, 8
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%t1 = and i32 %b, 8
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%t2 = icmp eq i32 %t0, %t1
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%t3 = zext i1 %t2 to i32
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ret i32 %t3
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}
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define i32 @test3(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: @test3(
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; CHECK-NEXT: [[T2_UNSHIFTED:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T2_UNSHIFTED]], -1
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; CHECK-NEXT: [[T2_UNSHIFTED_LOBIT_NOT:%.*]] = lshr i32 [[TMP1]], 31
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; CHECK-NEXT: ret i32 [[T2_UNSHIFTED_LOBIT_NOT]]
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;
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%t0 = lshr i32 %a, 31
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%t1 = lshr i32 %b, 31
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%t2 = icmp eq i32 %t0, %t1
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%t3 = zext i1 %t2 to i32
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ret i32 %t3
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}
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; TODO this should optimize but doesn't due to missing vector support in InstCombiner::foldICmpEquality.
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define <2 x i32> @test3vec(<2 x i32> %a, <2 x i32> %b) nounwind readnone {
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; CHECK-LABEL: @test3vec(
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; CHECK-NEXT: [[T0:%.*]] = lshr <2 x i32> [[A:%.*]], <i32 31, i32 31>
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; CHECK-NEXT: [[T1:%.*]] = lshr <2 x i32> [[B:%.*]], <i32 31, i32 31>
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; CHECK-NEXT: [[T2:%.*]] = icmp eq <2 x i32> [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = zext <2 x i1> [[T2]] to <2 x i32>
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; CHECK-NEXT: ret <2 x i32> [[T3]]
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;
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%t0 = lshr <2 x i32> %a, <i32 31, i32 31>
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%t1 = lshr <2 x i32> %b, <i32 31, i32 31>
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%t2 = icmp eq <2 x i32> %t0, %t1
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%t3 = zext <2 x i1> %t2 to <2 x i32>
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ret <2 x i32> %t3
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}
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; Variation on @test3: checking the 2nd bit in a situation where the 5th bit
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; is one, not zero.
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define i32 @test3i(i32 %a, i32 %b) nounwind readnone {
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; CHECK-LABEL: @test3i(
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; CHECK-NEXT: [[T01:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[T01]], -1
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; CHECK-NEXT: [[T01_LOBIT_NOT:%.*]] = lshr i32 [[TMP1]], 31
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; CHECK-NEXT: ret i32 [[T01_LOBIT_NOT]]
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;
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%t0 = lshr i32 %a, 29
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%t1 = lshr i32 %b, 29
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%t2 = or i32 %t0, 35
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%t3 = or i32 %t1, 35
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%t4 = icmp eq i32 %t2, %t3
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%t5 = zext i1 %t4 to i32
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ret i32 %t5
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}
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define i1 @test4a(i32 %a) {
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; CHECK-LABEL: @test4a(
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; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[A:%.*]], 1
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; CHECK-NEXT: ret i1 [[C]]
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;
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%l = ashr i32 %a, 31
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%na = sub i32 0, %a
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%r = lshr i32 %na, 31
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%signum = or i32 %l, %r
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%c = icmp slt i32 %signum, 1
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ret i1 %c
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}
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define <2 x i1> @test4a_vec(<2 x i32> %a) {
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; CHECK-LABEL: @test4a_vec(
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; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i32> [[A:%.*]], <i32 1, i32 1>
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; CHECK-NEXT: ret <2 x i1> [[C]]
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;
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%l = ashr <2 x i32> %a, <i32 31, i32 31>
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%na = sub <2 x i32> zeroinitializer, %a
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%r = lshr <2 x i32> %na, <i32 31, i32 31>
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%signum = or <2 x i32> %l, %r
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%c = icmp slt <2 x i32> %signum, <i32 1, i32 1>
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ret <2 x i1> %c
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}
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define i1 @test4b(i64 %a) {
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; CHECK-LABEL: @test4b(
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; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[A:%.*]], 1
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; CHECK-NEXT: ret i1 [[C]]
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;
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%l = ashr i64 %a, 63
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%na = sub i64 0, %a
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%r = lshr i64 %na, 63
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%signum = or i64 %l, %r
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%c = icmp slt i64 %signum, 1
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ret i1 %c
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}
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define i1 @test4c(i64 %a) {
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; CHECK-LABEL: @test4c(
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; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[A:%.*]], 1
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; CHECK-NEXT: ret i1 [[C]]
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;
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%l = ashr i64 %a, 63
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%na = sub i64 0, %a
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%r = lshr i64 %na, 63
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%signum = or i64 %l, %r
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%signum.trunc = trunc i64 %signum to i32
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%c = icmp slt i32 %signum.trunc, 1
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ret i1 %c
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}
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define <2 x i1> @test4c_vec(<2 x i64> %a) {
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; CHECK-LABEL: @test4c_vec(
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; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> [[A:%.*]], <i64 1, i64 1>
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; CHECK-NEXT: ret <2 x i1> [[C]]
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;
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%l = ashr <2 x i64> %a, <i64 63, i64 63>
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%na = sub <2 x i64> zeroinitializer, %a
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%r = lshr <2 x i64> %na, <i64 63, i64 63>
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%signum = or <2 x i64> %l, %r
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%signum.trunc = trunc <2 x i64> %signum to <2 x i32>
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%c = icmp slt <2 x i32> %signum.trunc, <i32 1, i32 1>
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ret <2 x i1> %c
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}
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; PR49866
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define i1 @shift_trunc_signbit_test(i32 %x) {
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; CHECK-LABEL: @shift_trunc_signbit_test(
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; CHECK-NEXT: [[R:%.*]] = icmp slt i32 [[X:%.*]], 0
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; CHECK-NEXT: ret i1 [[R]]
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;
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%sh = lshr i32 %x, 24
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%tr = trunc i32 %sh to i8
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%r = icmp slt i8 %tr, 0
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ret i1 %r
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}
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define <2 x i1> @shift_trunc_signbit_test_vec_uses(<2 x i17> %x, <2 x i17>* %p1, <2 x i13>* %p2) {
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; CHECK-LABEL: @shift_trunc_signbit_test_vec_uses(
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; CHECK-NEXT: [[SH:%.*]] = lshr <2 x i17> [[X:%.*]], <i17 4, i17 4>
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; CHECK-NEXT: store <2 x i17> [[SH]], <2 x i17>* [[P1:%.*]], align 8
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; CHECK-NEXT: [[TR:%.*]] = trunc <2 x i17> [[SH]] to <2 x i13>
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; CHECK-NEXT: store <2 x i13> [[TR]], <2 x i13>* [[P2:%.*]], align 4
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; CHECK-NEXT: [[R:%.*]] = icmp sgt <2 x i17> [[X]], <i17 -1, i17 -1>
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; CHECK-NEXT: ret <2 x i1> [[R]]
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;
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%sh = lshr <2 x i17> %x, <i17 4, i17 4>
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store <2 x i17> %sh, <2 x i17>* %p1
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%tr = trunc <2 x i17> %sh to <2 x i13>
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store <2 x i13> %tr, <2 x i13>* %p2
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%r = icmp sgt <2 x i13> %tr, <i13 -1, i13 -1>
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ret <2 x i1> %r
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}
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; negative test - but this reduces with a mask op
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define i1 @shift_trunc_wrong_shift(i32 %x) {
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; CHECK-LABEL: @shift_trunc_wrong_shift(
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; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[X:%.*]], 1073741824
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; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP1]], 0
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; CHECK-NEXT: ret i1 [[R]]
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;
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%sh = lshr i32 %x, 23
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%tr = trunc i32 %sh to i8
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%r = icmp slt i8 %tr, 0
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ret i1 %r
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}
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; negative test
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define i1 @shift_trunc_wrong_cmp(i32 %x) {
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; CHECK-LABEL: @shift_trunc_wrong_cmp(
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; CHECK-NEXT: [[SH:%.*]] = lshr i32 [[X:%.*]], 24
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; CHECK-NEXT: [[TR:%.*]] = trunc i32 [[SH]] to i8
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; CHECK-NEXT: [[R:%.*]] = icmp slt i8 [[TR]], 1
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; CHECK-NEXT: ret i1 [[R]]
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;
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%sh = lshr i32 %x, 24
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%tr = trunc i32 %sh to i8
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%r = icmp slt i8 %tr, 1
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ret i1 %r
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}
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