227 lines
7.0 KiB
LLVM
227 lines
7.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i1 @pr40493(i32 %area) {
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; CHECK-LABEL: @pr40493(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AREA:%.*]], 12
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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entry:
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%mul = mul i32 %area, 12
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%rem = and i32 %mul, 4
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%cmp = icmp eq i32 %rem, 0
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ret i1 %cmp
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}
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define i1 @pr40493_neg1(i32 %area) {
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; CHECK-LABEL: @pr40493_neg1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AREA:%.*]], 11
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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entry:
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%mul = mul i32 %area, 11
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%rem = and i32 %mul, 4
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%cmp = icmp eq i32 %rem, 0
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ret i1 %cmp
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}
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define i1 @pr40493_neg2(i32 %area) {
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; CHECK-LABEL: @pr40493_neg2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AREA:%.*]], 12
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 12
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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entry:
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%mul = mul i32 %area, 12
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%rem = and i32 %mul, 15
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%cmp = icmp eq i32 %rem, 0
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ret i1 %cmp
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}
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define i32 @pr40493_neg3(i32 %area) {
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; CHECK-LABEL: @pr40493_neg3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[AREA:%.*]], 12
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; CHECK-NEXT: [[REM:%.*]] = and i32 [[MUL]], 4
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; CHECK-NEXT: ret i32 [[REM]]
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;
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entry:
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%mul = mul i32 %area, 12
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%rem = and i32 %mul, 4
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ret i32 %rem
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}
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define <4 x i1> @pr40493_vec1(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 12, i32 12>
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 4>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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entry:
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 12>
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%rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 4>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define <4 x i1> @pr40493_vec2(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 12, i32 undef>
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 4>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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entry:
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 undef>
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%rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 4>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define <4 x i1> @pr40493_vec3(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 12, i32 12>
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 undef>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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entry:
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 12>
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%rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 undef>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define <4 x i1> @pr40493_vec4(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec4(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 12, i32 undef>
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 4, i32 4, i32 4, i32 undef>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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entry:
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 12, i32 undef>
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%rem = and <4 x i32> %mul, <i32 4, i32 4, i32 4, i32 undef>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define <4 x i1> @pr40493_vec5(<4 x i32> %area) {
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; CHECK-LABEL: @pr40493_vec5(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[AREA:%.*]], <i32 12, i32 12, i32 20, i32 20>
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; CHECK-NEXT: [[REM:%.*]] = and <4 x i32> [[MUL]], <i32 2, i32 4, i32 2, i32 4>
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq <4 x i32> [[REM]], zeroinitializer
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; CHECK-NEXT: ret <4 x i1> [[CMP]]
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;
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entry:
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%mul = mul <4 x i32> %area, <i32 12, i32 12, i32 20, i32 20>
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%rem = and <4 x i32> %mul, <i32 2, i32 4, i32 2, i32 4>
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%cmp = icmp eq <4 x i32> %rem, zeroinitializer
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ret <4 x i1> %cmp
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}
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define i1 @pr51551(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[Y:%.*]], -8
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; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP0]], 1
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], [[X:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[MUL]], 3
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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entry:
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%0 = and i32 %y, -7
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%1 = or i32 %0, 1
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%mul = mul nsw i32 %1, %x
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%and = and i32 %mul, 3
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define i1 @pr51551_2(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551_2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[Y:%.*]], -8
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; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP0]], 1
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], [[X:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[MUL]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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entry:
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%0 = and i32 %y, -7
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%1 = or i32 %0, 1
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%mul = mul nsw i32 %1, %x
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%and = and i32 %mul, 1
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define i1 @pr51551_neg1(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551_neg1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[Y:%.*]], -4
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; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP0]], 1
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], [[X:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[MUL]], 7
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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entry:
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%0 = and i32 %y, -3
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%1 = or i32 %0, 1
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%mul = mul nsw i32 %1, %x
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%and = and i32 %mul, 7
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define i1 @pr51551_neg2(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551_neg2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[Y:%.*]], -7
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP0]], [[X:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[MUL]], 7
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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entry:
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%0 = and i32 %y, -7
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%mul = mul nsw i32 %0, %x
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%and = and i32 %mul, 7
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%cmp = icmp eq i32 %and, 0
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ret i1 %cmp
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}
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define i32 @pr51551_neg3(i32 %x, i32 %y) {
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; CHECK-LABEL: @pr51551_neg3(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[Y:%.*]], -8
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; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[TMP0]], 1
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP1]], [[X:%.*]]
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[MUL]], 7
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; CHECK-NEXT: ret i32 [[AND]]
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;
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entry:
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%0 = and i32 %y, -7
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%1 = or i32 %0, 1
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%mul = mul nsw i32 %1, %x
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%and = and i32 %mul, 7
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ret i32 %and
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}
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