247 lines
9.0 KiB
LLVM
247 lines
9.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i8 @zext_or_icmp_icmp(i8 %a, i8 %b) {
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; CHECK-LABEL: @zext_or_icmp_icmp(
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; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 1
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; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 0
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; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 0
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; CHECK-NEXT: [[BOTHCOND:%.*]] = or i1 [[TOBOOL1]], [[TOBOOL2]]
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i8
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; CHECK-NEXT: ret i8 [[ZEXT]]
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;
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%mask = and i8 %a, 1
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%toBool1 = icmp eq i8 %mask, 0
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%toBool2 = icmp eq i8 %b, 0
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%bothCond = or i1 %toBool1, %toBool2
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%zext = zext i1 %bothCond to i8
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ret i8 %zext
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}
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define i8 @zext_or_icmp_icmp_logical(i8 %a, i8 %b) {
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; CHECK-LABEL: @zext_or_icmp_icmp_logical(
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; CHECK-NEXT: [[MASK:%.*]] = and i8 [[A:%.*]], 1
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; CHECK-NEXT: [[TOBOOL1:%.*]] = icmp eq i8 [[MASK]], 0
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; CHECK-NEXT: [[TOBOOL2:%.*]] = icmp eq i8 [[B:%.*]], 0
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; CHECK-NEXT: [[BOTHCOND:%.*]] = select i1 [[TOBOOL1]], i1 true, i1 [[TOBOOL2]]
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[BOTHCOND]] to i8
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; CHECK-NEXT: ret i8 [[ZEXT]]
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;
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%mask = and i8 %a, 1
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%toBool1 = icmp eq i8 %mask, 0
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%toBool2 = icmp eq i8 %b, 0
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%bothCond = select i1 %toBool1, i1 true, i1 %toBool2
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%zext = zext i1 %bothCond to i8
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ret i8 %zext
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}
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; Here, widening the or from i1 to i32 and removing one of the icmps would
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; widen an undef value (created by the out-of-range shift), increasing the
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; range of valid values for the return, so we can't do it.
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define i32 @dont_widen_undef() {
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; CHECK-LABEL: @dont_widen_undef(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[BLOCK2:%.*]]
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; CHECK: block1:
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; CHECK-NEXT: br label [[BLOCK2]]
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; CHECK: block2:
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; CHECK-NEXT: [[CMP_I:%.*]] = phi i1 [ false, [[BLOCK1:%.*]] ], [ true, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[CMP115:%.*]] = phi i1 [ true, [[BLOCK1]] ], [ false, [[ENTRY]] ]
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; CHECK-NEXT: [[CMP1:%.*]] = or i1 [[CMP_I]], [[CMP115]]
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; CHECK-NEXT: [[CONV2:%.*]] = zext i1 [[CMP1]] to i32
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; CHECK-NEXT: ret i32 [[CONV2]]
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;
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entry:
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br label %block2
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block1:
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br label %block2
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block2:
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%m.011 = phi i32 [ 33, %entry ], [ 0, %block1 ]
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%cmp.i = icmp ugt i32 %m.011, 1
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%m.1.op = lshr i32 1, %m.011
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%sext.mask = and i32 %m.1.op, 65535
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%cmp115 = icmp ne i32 %sext.mask, 0
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%cmp1 = or i1 %cmp.i, %cmp115
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%conv2 = zext i1 %cmp1 to i32
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ret i32 %conv2
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}
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define i32 @dont_widen_undef_logical() {
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; CHECK-LABEL: @dont_widen_undef_logical(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[BLOCK2:%.*]]
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; CHECK: block1:
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; CHECK-NEXT: br label [[BLOCK2]]
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; CHECK: block2:
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; CHECK-NEXT: [[CMP_I:%.*]] = phi i1 [ false, [[BLOCK1:%.*]] ], [ true, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[CMP115:%.*]] = phi i1 [ true, [[BLOCK1]] ], [ false, [[ENTRY]] ]
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; CHECK-NEXT: [[CMP1:%.*]] = or i1 [[CMP_I]], [[CMP115]]
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; CHECK-NEXT: [[CONV2:%.*]] = zext i1 [[CMP1]] to i32
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; CHECK-NEXT: ret i32 [[CONV2]]
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;
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entry:
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br label %block2
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block1:
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br label %block2
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block2:
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%m.011 = phi i32 [ 33, %entry ], [ 0, %block1 ]
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%cmp.i = icmp ugt i32 %m.011, 1
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%m.1.op = lshr i32 1, %m.011
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%sext.mask = and i32 %m.1.op, 65535
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%cmp115 = icmp ne i32 %sext.mask, 0
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%cmp1 = select i1 %cmp.i, i1 true, i1 %cmp115
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%conv2 = zext i1 %cmp1 to i32
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ret i32 %conv2
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}
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; This should not end with more instructions than it started from.
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define i32 @PR49475(i32 %x, i16 %y) {
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; CHECK-LABEL: @PR49475(
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; CHECK-NEXT: [[M:%.*]] = and i16 [[Y:%.*]], 1
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; CHECK-NEXT: [[B1:%.*]] = icmp eq i32 [[X:%.*]], 0
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; CHECK-NEXT: [[B2:%.*]] = icmp eq i16 [[M]], 0
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; CHECK-NEXT: [[T1:%.*]] = or i1 [[B1]], [[B2]]
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; CHECK-NEXT: [[Z:%.*]] = zext i1 [[T1]] to i32
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; CHECK-NEXT: ret i32 [[Z]]
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;
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%m = and i16 %y, 1
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%b1 = icmp eq i32 %x, 0
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%b2 = icmp eq i16 %m, 0
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%t1 = or i1 %b1, %b2
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%z = zext i1 %t1 to i32
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ret i32 %z
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}
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; This would infinite-loop.
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define i8 @PR49475_infloop(i32 %t0, i16 %insert, i64 %e, i8 %i162) {
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; CHECK-LABEL: @PR49475_infloop(
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; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[T0:%.*]], 0
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; CHECK-NEXT: [[B2:%.*]] = icmp eq i16 [[INSERT:%.*]], 0
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; CHECK-NEXT: [[T1:%.*]] = or i1 [[B]], [[B2]]
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; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[T1]] to i32
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[EXT]], [[T0]]
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; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[AND]], 140
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; CHECK-NEXT: [[XOR1:%.*]] = zext i32 [[TMP1]] to i64
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; CHECK-NEXT: [[CONV16:%.*]] = sext i8 [[I162:%.*]] to i64
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; CHECK-NEXT: [[SUB17:%.*]] = sub i64 [[CONV16]], [[E:%.*]]
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; CHECK-NEXT: [[SEXT:%.*]] = shl i64 [[SUB17]], 32
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; CHECK-NEXT: [[CONV18:%.*]] = ashr exact i64 [[SEXT]], 32
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; CHECK-NEXT: [[CMP:%.*]] = icmp sle i64 [[CONV18]], [[XOR1]]
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; CHECK-NEXT: [[CONV19:%.*]] = zext i1 [[CMP]] to i16
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; CHECK-NEXT: [[OR21:%.*]] = or i16 [[CONV19]], [[INSERT]]
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; CHECK-NEXT: [[TRUNC44:%.*]] = trunc i16 [[OR21]] to i8
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; CHECK-NEXT: [[INC:%.*]] = or i8 [[TRUNC44]], [[I162]]
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; CHECK-NEXT: [[TOBOOL23_NOT:%.*]] = icmp eq i16 [[OR21]], 0
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; CHECK-NEXT: call void @llvm.assume(i1 [[TOBOOL23_NOT]])
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; CHECK-NEXT: ret i8 [[INC]]
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;
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%b = icmp eq i32 %t0, 0
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%b2 = icmp eq i16 %insert, 0
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%t1 = or i1 %b, %b2
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%ext = zext i1 %t1 to i32
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%and = and i32 %t0, %ext
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%conv13 = zext i32 %and to i64
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%xor = xor i64 %conv13, 140
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%conv16 = sext i8 %i162 to i64
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%sub17 = sub i64 %conv16, %e
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%sext = shl i64 %sub17, 32
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%conv18 = ashr exact i64 %sext, 32
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%cmp = icmp sge i64 %xor, %conv18
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%conv19 = zext i1 %cmp to i16
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%or21 = or i16 %insert, %conv19
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%trunc44 = trunc i16 %or21 to i8
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%inc = add i8 %i162, %trunc44
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%tobool23.not = icmp eq i16 %or21, 0
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call void @llvm.assume(i1 %tobool23.not)
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ret i8 %inc
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}
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; This would infinite loop because knownbits changed between checking
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; if a transform was profitable and actually doing the transform.
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define i1 @PR51762(i32 *%i, i32 %t0, i16 %t1, i64* %p, i32* %d, i32* %f, i32 %p2) {
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; CHECK-LABEL: @PR51762(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[FOR_COND:%.*]]
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; CHECK: for.cond:
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; CHECK-NEXT: [[I_SROA_8_0:%.*]] = phi i32 [ undef, [[ENTRY:%.*]] ], [ [[I_SROA_8_0_EXTRACT_TRUNC:%.*]], [[COND_TRUE:%.*]] ]
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; CHECK-NEXT: br i1 undef, label [[COND_TRUE]], label [[FOR_END11:%.*]]
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; CHECK: cond.true:
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; CHECK-NEXT: [[I_SROA_8_0_EXTRACT_TRUNC]] = ashr i32 [[T0:%.*]], 31
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; CHECK-NEXT: br label [[FOR_COND]]
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; CHECK: for.end11:
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; CHECK-NEXT: [[S1:%.*]] = sext i16 [[T1:%.*]] to i64
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; CHECK-NEXT: [[SROA38:%.*]] = load i32, i32* [[I:%.*]], align 8
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; CHECK-NEXT: [[INSERT_EXT51:%.*]] = zext i32 [[I_SROA_8_0]] to i64
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; CHECK-NEXT: [[INSERT_SHIFT52:%.*]] = shl nuw i64 [[INSERT_EXT51]], 32
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; CHECK-NEXT: [[INSERT_EXT39:%.*]] = zext i32 [[SROA38]] to i64
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; CHECK-NEXT: [[INSERT_INSERT41:%.*]] = or i64 [[INSERT_SHIFT52]], [[INSERT_EXT39]]
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; CHECK-NEXT: [[REM:%.*]] = urem i64 [[S1]], [[INSERT_INSERT41]]
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; CHECK-NEXT: [[NE:%.*]] = icmp ne i64 [[REM]], 0
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[INSERT_INSERT41]], 0
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; CHECK-NEXT: [[SPEC_SELECT57:%.*]] = or i1 [[NE]], [[CMP]]
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; CHECK-NEXT: [[LOR_EXT:%.*]] = zext i1 [[SPEC_SELECT57]] to i32
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; CHECK-NEXT: [[T2:%.*]] = load i32, i32* [[D:%.*]], align 4
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; CHECK-NEXT: [[CONV15:%.*]] = sext i16 [[T1]] to i32
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; CHECK-NEXT: [[CMP16:%.*]] = icmp sge i32 [[T2]], [[CONV15]]
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; CHECK-NEXT: [[CONV17:%.*]] = zext i1 [[CMP16]] to i32
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; CHECK-NEXT: [[T3:%.*]] = load i32, i32* [[F:%.*]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[T3]], [[CONV17]]
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; CHECK-NEXT: store i32 [[ADD]], i32* [[F]], align 4
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; CHECK-NEXT: [[REM18:%.*]] = srem i32 [[LOR_EXT]], [[ADD]]
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; CHECK-NEXT: [[CONV19:%.*]] = zext i32 [[REM18]] to i64
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; CHECK-NEXT: store i32 0, i32* [[D]], align 8
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; CHECK-NEXT: [[R:%.*]] = icmp ult i64 [[INSERT_INSERT41]], [[CONV19]]
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; CHECK-NEXT: call void @llvm.assume(i1 [[R]])
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; CHECK-NEXT: ret i1 true
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;
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entry:
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br label %for.cond
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for.cond:
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%i.sroa.8.0 = phi i32 [ undef, %entry ], [ %i.sroa.8.0.extract.trunc, %cond.true ]
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br i1 undef, label %cond.true, label %for.end11
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cond.true:
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%i.sroa.8.0.extract.trunc = ashr i32 %t0, 31
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br label %for.cond
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for.end11:
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%s1 = sext i16 %t1 to i64
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%sroa38 = load i32, i32* %i, align 8
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%insert.ext51 = zext i32 %i.sroa.8.0 to i64
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%insert.shift52 = shl nuw i64 %insert.ext51, 32
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%insert.ext39 = zext i32 %sroa38 to i64
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%insert.insert41 = or i64 %insert.shift52, %insert.ext39
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%rem = urem i64 %s1, %insert.insert41
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%ne = icmp ne i64 %rem, 0
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%cmp = icmp eq i64 %insert.insert41, 0
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%spec.select57 = or i1 %ne, %cmp
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%lor.ext = zext i1 %spec.select57 to i32
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%t2 = load i32, i32* %d, align 4
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%conv15 = sext i16 %t1 to i32
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%cmp16 = icmp sge i32 %t2, %conv15
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%conv17 = zext i1 %cmp16 to i32
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%t3 = load i32, i32* %f, align 4
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%add = add nsw i32 %t3, %conv17
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store i32 %add, i32* %f, align 4
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%rem18 = srem i32 %lor.ext, %add
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%conv19 = zext i32 %rem18 to i64
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%div = udiv i64 %insert.insert41, %conv19
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%trunc33 = trunc i64 %div to i32
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store i32 %trunc33, i32* %d, align 8
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%r = icmp ult i64 %insert.insert41, %conv19
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call void @llvm.assume(i1 %r)
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ret i1 %r
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}
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declare void @llvm.assume(i1 noundef)
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