Simon Pilgrim 67cce1ceee [X86] Adjust some IceLake fp shuffle schedule classes (PR48110) ... The IceLake scheduler model is still mainly a copy of the SkylakeServer model. This patch adjusts the fp shuffle classes to account for most instructions now working on Port 1 as well as Port 5. This is based off Agner + uops.info as well as the PR48110 report. Differential Revision: https://reviews.llvm.org/D115752		2021-12-19 13:00:11 +00:00
..
AArch64	[AArch64] Model Cortex-A55 Q register NEON instructions	2021-09-29 16:55:31 +01:00
AMDGPU	[MCA] Adding an AMDGPUCustomBehaviour implementation.	2021-08-24 13:33:58 -07:00
ARM	[MCA][InstrBuilder] Check for the presence of flag VariadicOpsAreDefs.	2021-06-15 09:52:38 +01:00
JSON/X86	[llvm-mca][JSON] Store extra information about driver flags used for the simulation	2021-07-16 09:18:40 +02:00
SystemZ	…
X86	[X86] Adjust some IceLake fp shuffle schedule classes (PR48110)	2021-12-19 13:00:11 +00:00
invalid_input_file_name.test	[test] Use host platform specific error message substitution in lit tests	2021-01-29 07:16:30 -05:00
lit.local.cfg	…