693 lines
19 KiB
C++
693 lines
19 KiB
C++
//==- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface --*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
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#include "AMDGPUArgumentUsageInfo.h"
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#include "AMDGPUMachineFunction.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/SparseBitVector.h"
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#include "llvm/CodeGen/MIRYamlMapping.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <array>
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#include <cassert>
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#include <utility>
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#include <vector>
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namespace llvm {
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class MachineFrameInfo;
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class MachineFunction;
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class TargetRegisterClass;
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class AMDGPUImagePseudoSourceValue : public PseudoSourceValue {
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public:
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// TODO: Is the img rsrc useful?
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explicit AMDGPUImagePseudoSourceValue(const TargetInstrInfo &TII) :
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PseudoSourceValue(PseudoSourceValue::TargetCustom, TII) {}
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bool isConstant(const MachineFrameInfo *) const override {
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// This should probably be true for most images, but we will start by being
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// conservative.
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return false;
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}
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bool isAliased(const MachineFrameInfo *) const override {
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return true;
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}
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bool mayAlias(const MachineFrameInfo *) const override {
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return true;
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}
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};
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class AMDGPUBufferPseudoSourceValue : public PseudoSourceValue {
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public:
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explicit AMDGPUBufferPseudoSourceValue(const TargetInstrInfo &TII) :
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PseudoSourceValue(PseudoSourceValue::TargetCustom, TII) { }
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bool isConstant(const MachineFrameInfo *) const override {
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// This should probably be true for most images, but we will start by being
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// conservative.
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return false;
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}
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bool isAliased(const MachineFrameInfo *) const override {
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return true;
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}
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bool mayAlias(const MachineFrameInfo *) const override {
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return true;
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}
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};
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namespace yaml {
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struct SIMachineFunctionInfo final : public yaml::MachineFunctionInfo {
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uint64_t ExplicitKernArgSize = 0;
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unsigned MaxKernArgAlign = 0;
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unsigned LDSSize = 0;
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bool IsEntryFunction = false;
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bool NoSignedZerosFPMath = false;
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bool MemoryBound = false;
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bool WaveLimiter = false;
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StringValue ScratchRSrcReg = "$private_rsrc_reg";
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StringValue ScratchWaveOffsetReg = "$scratch_wave_offset_reg";
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StringValue FrameOffsetReg = "$fp_reg";
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StringValue StackPtrOffsetReg = "$sp_reg";
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SIMachineFunctionInfo() = default;
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SIMachineFunctionInfo(const llvm::SIMachineFunctionInfo &,
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const TargetRegisterInfo &TRI);
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void mappingImpl(yaml::IO &YamlIO) override;
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~SIMachineFunctionInfo() = default;
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};
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template <> struct MappingTraits<SIMachineFunctionInfo> {
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static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI) {
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YamlIO.mapOptional("explicitKernArgSize", MFI.ExplicitKernArgSize,
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UINT64_C(0));
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YamlIO.mapOptional("maxKernArgAlign", MFI.MaxKernArgAlign, 0u);
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YamlIO.mapOptional("ldsSize", MFI.LDSSize, 0u);
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YamlIO.mapOptional("isEntryFunction", MFI.IsEntryFunction, false);
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YamlIO.mapOptional("noSignedZerosFPMath", MFI.NoSignedZerosFPMath, false);
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YamlIO.mapOptional("memoryBound", MFI.MemoryBound, false);
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YamlIO.mapOptional("waveLimiter", MFI.WaveLimiter, false);
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YamlIO.mapOptional("scratchRSrcReg", MFI.ScratchRSrcReg,
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StringValue("$private_rsrc_reg"));
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YamlIO.mapOptional("scratchWaveOffsetReg", MFI.ScratchWaveOffsetReg,
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StringValue("$scratch_wave_offset_reg"));
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YamlIO.mapOptional("frameOffsetReg", MFI.FrameOffsetReg,
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StringValue("$fp_reg"));
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YamlIO.mapOptional("stackPtrOffsetReg", MFI.StackPtrOffsetReg,
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StringValue("$sp_reg"));
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}
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};
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} // end namespace yaml
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/// This class keeps track of the SPI_SP_INPUT_ADDR config register, which
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/// tells the hardware which interpolation parameters to load.
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class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
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friend class GCNTargetMachine;
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unsigned TIDReg = AMDGPU::NoRegister;
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// Registers that may be reserved for spilling purposes. These may be the same
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// as the input registers.
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unsigned ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
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unsigned ScratchWaveOffsetReg = AMDGPU::SCRATCH_WAVE_OFFSET_REG;
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// This is the current function's incremented size from the kernel's scratch
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// wave offset register. For an entry function, this is exactly the same as
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// the ScratchWaveOffsetReg.
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unsigned FrameOffsetReg = AMDGPU::FP_REG;
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// Top of the stack SGPR offset derived from the ScratchWaveOffsetReg.
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unsigned StackPtrOffsetReg = AMDGPU::SP_REG;
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AMDGPUFunctionArgInfo ArgInfo;
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// State of MODE register, assumed FP mode.
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AMDGPU::SIModeRegisterDefaults Mode;
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// Graphics info.
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unsigned PSInputAddr = 0;
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unsigned PSInputEnable = 0;
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/// Number of bytes of arguments this function has on the stack. If the callee
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/// is expected to restore the argument stack this should be a multiple of 16,
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/// all usable during a tail call.
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///
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/// The alternative would forbid tail call optimisation in some cases: if we
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/// want to transfer control from a function with 8-bytes of stack-argument
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/// space to a function with 16-bytes then misalignment of this value would
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/// make a stack adjustment necessary, which could not be undone by the
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/// callee.
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unsigned BytesInStackArgArea = 0;
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bool ReturnsVoid = true;
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// A pair of default/requested minimum/maximum flat work group sizes.
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// Minimum - first, maximum - second.
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std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
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// A pair of default/requested minimum/maximum number of waves per execution
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// unit. Minimum - first, maximum - second.
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std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
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DenseMap<const Value *,
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std::unique_ptr<const AMDGPUBufferPseudoSourceValue>> BufferPSVs;
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DenseMap<const Value *,
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std::unique_ptr<const AMDGPUImagePseudoSourceValue>> ImagePSVs;
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private:
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unsigned LDSWaveSpillSize = 0;
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unsigned NumUserSGPRs = 0;
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unsigned NumSystemSGPRs = 0;
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bool HasSpilledSGPRs = false;
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bool HasSpilledVGPRs = false;
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bool HasNonSpillStackObjects = false;
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bool IsStackRealigned = false;
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unsigned NumSpilledSGPRs = 0;
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unsigned NumSpilledVGPRs = 0;
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// Feature bits required for inputs passed in user SGPRs.
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bool PrivateSegmentBuffer : 1;
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bool DispatchPtr : 1;
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bool QueuePtr : 1;
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bool KernargSegmentPtr : 1;
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bool DispatchID : 1;
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bool FlatScratchInit : 1;
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// Feature bits required for inputs passed in system SGPRs.
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bool WorkGroupIDX : 1; // Always initialized.
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bool WorkGroupIDY : 1;
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bool WorkGroupIDZ : 1;
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bool WorkGroupInfo : 1;
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bool PrivateSegmentWaveByteOffset : 1;
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bool WorkItemIDX : 1; // Always initialized.
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bool WorkItemIDY : 1;
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bool WorkItemIDZ : 1;
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// Private memory buffer
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// Compute directly in sgpr[0:1]
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// Other shaders indirect 64-bits at sgpr[0:1]
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bool ImplicitBufferPtr : 1;
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// Pointer to where the ABI inserts special kernel arguments separate from the
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// user arguments. This is an offset from the KernargSegmentPtr.
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bool ImplicitArgPtr : 1;
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// The hard-wired high half of the address of the global information table
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// for AMDPAL OS type. 0xffffffff represents no hard-wired high half, since
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// current hardware only allows a 16 bit value.
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unsigned GITPtrHigh;
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unsigned HighBitsOf32BitAddress;
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// Current recorded maximum possible occupancy.
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unsigned Occupancy;
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MCPhysReg getNextUserSGPR() const;
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MCPhysReg getNextSystemSGPR() const;
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public:
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struct SpilledReg {
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unsigned VGPR = 0;
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int Lane = -1;
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SpilledReg() = default;
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SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {}
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bool hasLane() { return Lane != -1;}
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bool hasReg() { return VGPR != 0;}
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};
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struct SGPRSpillVGPRCSR {
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// VGPR used for SGPR spills
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unsigned VGPR;
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// If the VGPR is a CSR, the stack slot used to save/restore it in the
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// prolog/epilog.
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Optional<int> FI;
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SGPRSpillVGPRCSR(unsigned V, Optional<int> F) : VGPR(V), FI(F) {}
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};
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SparseBitVector<> WWMReservedRegs;
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void ReserveWWMRegister(unsigned reg) { WWMReservedRegs.set(reg); }
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private:
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// SGPR->VGPR spilling support.
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using SpillRegMask = std::pair<unsigned, unsigned>;
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// Track VGPR + wave index for each subregister of the SGPR spilled to
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// frameindex key.
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DenseMap<int, std::vector<SpilledReg>> SGPRToVGPRSpills;
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unsigned NumVGPRSpillLanes = 0;
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SmallVector<SGPRSpillVGPRCSR, 2> SpillVGPRs;
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public:
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SIMachineFunctionInfo(const MachineFunction &MF);
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bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI);
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ArrayRef<SpilledReg> getSGPRToVGPRSpills(int FrameIndex) const {
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auto I = SGPRToVGPRSpills.find(FrameIndex);
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return (I == SGPRToVGPRSpills.end()) ?
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ArrayRef<SpilledReg>() : makeArrayRef(I->second);
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}
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ArrayRef<SGPRSpillVGPRCSR> getSGPRSpillVGPRs() const {
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return SpillVGPRs;
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}
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AMDGPU::SIModeRegisterDefaults getMode() const {
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return Mode;
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}
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bool allocateSGPRSpillToVGPR(MachineFunction &MF, int FI);
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void removeSGPRToVGPRFrameIndices(MachineFrameInfo &MFI);
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bool hasCalculatedTID() const { return TIDReg != 0; };
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unsigned getTIDReg() const { return TIDReg; };
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void setTIDReg(unsigned Reg) { TIDReg = Reg; }
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unsigned getBytesInStackArgArea() const {
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return BytesInStackArgArea;
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}
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void setBytesInStackArgArea(unsigned Bytes) {
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BytesInStackArgArea = Bytes;
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}
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// Add user SGPRs.
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unsigned addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
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unsigned addDispatchPtr(const SIRegisterInfo &TRI);
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unsigned addQueuePtr(const SIRegisterInfo &TRI);
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unsigned addKernargSegmentPtr(const SIRegisterInfo &TRI);
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unsigned addDispatchID(const SIRegisterInfo &TRI);
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unsigned addFlatScratchInit(const SIRegisterInfo &TRI);
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unsigned addImplicitBufferPtr(const SIRegisterInfo &TRI);
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// Add system SGPRs.
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unsigned addWorkGroupIDX() {
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ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
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NumSystemSGPRs += 1;
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return ArgInfo.WorkGroupIDX.getRegister();
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}
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unsigned addWorkGroupIDY() {
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ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
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NumSystemSGPRs += 1;
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return ArgInfo.WorkGroupIDY.getRegister();
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}
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unsigned addWorkGroupIDZ() {
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ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
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NumSystemSGPRs += 1;
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return ArgInfo.WorkGroupIDZ.getRegister();
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}
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unsigned addWorkGroupInfo() {
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ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
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NumSystemSGPRs += 1;
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return ArgInfo.WorkGroupInfo.getRegister();
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}
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// Add special VGPR inputs
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void setWorkItemIDX(ArgDescriptor Arg) {
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ArgInfo.WorkItemIDX = Arg;
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}
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void setWorkItemIDY(ArgDescriptor Arg) {
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ArgInfo.WorkItemIDY = Arg;
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}
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void setWorkItemIDZ(ArgDescriptor Arg) {
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ArgInfo.WorkItemIDZ = Arg;
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}
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unsigned addPrivateSegmentWaveByteOffset() {
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ArgInfo.PrivateSegmentWaveByteOffset
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= ArgDescriptor::createRegister(getNextSystemSGPR());
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NumSystemSGPRs += 1;
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return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
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}
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void setPrivateSegmentWaveByteOffset(unsigned Reg) {
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ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
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}
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bool hasPrivateSegmentBuffer() const {
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return PrivateSegmentBuffer;
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}
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bool hasDispatchPtr() const {
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return DispatchPtr;
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}
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bool hasQueuePtr() const {
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return QueuePtr;
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}
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bool hasKernargSegmentPtr() const {
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return KernargSegmentPtr;
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}
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bool hasDispatchID() const {
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return DispatchID;
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}
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bool hasFlatScratchInit() const {
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return FlatScratchInit;
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}
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bool hasWorkGroupIDX() const {
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return WorkGroupIDX;
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}
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bool hasWorkGroupIDY() const {
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return WorkGroupIDY;
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}
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bool hasWorkGroupIDZ() const {
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return WorkGroupIDZ;
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}
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bool hasWorkGroupInfo() const {
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return WorkGroupInfo;
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}
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bool hasPrivateSegmentWaveByteOffset() const {
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return PrivateSegmentWaveByteOffset;
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}
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bool hasWorkItemIDX() const {
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return WorkItemIDX;
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}
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bool hasWorkItemIDY() const {
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return WorkItemIDY;
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}
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bool hasWorkItemIDZ() const {
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return WorkItemIDZ;
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}
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bool hasImplicitArgPtr() const {
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return ImplicitArgPtr;
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}
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bool hasImplicitBufferPtr() const {
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return ImplicitBufferPtr;
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}
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AMDGPUFunctionArgInfo &getArgInfo() {
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return ArgInfo;
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}
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const AMDGPUFunctionArgInfo &getArgInfo() const {
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return ArgInfo;
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}
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std::pair<const ArgDescriptor *, const TargetRegisterClass *>
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getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
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return ArgInfo.getPreloadedValue(Value);
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}
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unsigned getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const {
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return ArgInfo.getPreloadedValue(Value).first->getRegister();
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}
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unsigned getGITPtrHigh() const {
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return GITPtrHigh;
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}
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unsigned get32BitAddressHighBits() const {
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return HighBitsOf32BitAddress;
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}
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unsigned getNumUserSGPRs() const {
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return NumUserSGPRs;
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}
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unsigned getNumPreloadedSGPRs() const {
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return NumUserSGPRs + NumSystemSGPRs;
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}
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unsigned getPrivateSegmentWaveByteOffsetSystemSGPR() const {
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return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
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}
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/// Returns the physical register reserved for use as the resource
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/// descriptor for scratch accesses.
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unsigned getScratchRSrcReg() const {
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return ScratchRSrcReg;
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}
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void setScratchRSrcReg(unsigned Reg) {
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assert(Reg != 0 && "Should never be unset");
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ScratchRSrcReg = Reg;
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}
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unsigned getScratchWaveOffsetReg() const {
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return ScratchWaveOffsetReg;
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}
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unsigned getFrameOffsetReg() const {
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return FrameOffsetReg;
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}
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void setStackPtrOffsetReg(unsigned Reg) {
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assert(Reg != 0 && "Should never be unset");
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StackPtrOffsetReg = Reg;
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}
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// Note the unset value for this is AMDGPU::SP_REG rather than
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// NoRegister. This is mostly a workaround for MIR tests where state that
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// can't be directly computed from the function is not preserved in serialized
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// MIR.
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unsigned getStackPtrOffsetReg() const {
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return StackPtrOffsetReg;
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}
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void setScratchWaveOffsetReg(unsigned Reg) {
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assert(Reg != 0 && "Should never be unset");
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ScratchWaveOffsetReg = Reg;
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if (isEntryFunction())
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FrameOffsetReg = ScratchWaveOffsetReg;
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}
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unsigned getQueuePtrUserSGPR() const {
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return ArgInfo.QueuePtr.getRegister();
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}
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unsigned getImplicitBufferPtrUserSGPR() const {
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return ArgInfo.ImplicitBufferPtr.getRegister();
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}
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bool hasSpilledSGPRs() const {
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return HasSpilledSGPRs;
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}
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void setHasSpilledSGPRs(bool Spill = true) {
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HasSpilledSGPRs = Spill;
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}
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bool hasSpilledVGPRs() const {
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return HasSpilledVGPRs;
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}
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void setHasSpilledVGPRs(bool Spill = true) {
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HasSpilledVGPRs = Spill;
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}
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bool hasNonSpillStackObjects() const {
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return HasNonSpillStackObjects;
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}
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void setHasNonSpillStackObjects(bool StackObject = true) {
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HasNonSpillStackObjects = StackObject;
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}
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bool isStackRealigned() const {
|
|
return IsStackRealigned;
|
|
}
|
|
|
|
void setIsStackRealigned(bool Realigned = true) {
|
|
IsStackRealigned = Realigned;
|
|
}
|
|
|
|
unsigned getNumSpilledSGPRs() const {
|
|
return NumSpilledSGPRs;
|
|
}
|
|
|
|
unsigned getNumSpilledVGPRs() const {
|
|
return NumSpilledVGPRs;
|
|
}
|
|
|
|
void addToSpilledSGPRs(unsigned num) {
|
|
NumSpilledSGPRs += num;
|
|
}
|
|
|
|
void addToSpilledVGPRs(unsigned num) {
|
|
NumSpilledVGPRs += num;
|
|
}
|
|
|
|
unsigned getPSInputAddr() const {
|
|
return PSInputAddr;
|
|
}
|
|
|
|
unsigned getPSInputEnable() const {
|
|
return PSInputEnable;
|
|
}
|
|
|
|
bool isPSInputAllocated(unsigned Index) const {
|
|
return PSInputAddr & (1 << Index);
|
|
}
|
|
|
|
void markPSInputAllocated(unsigned Index) {
|
|
PSInputAddr |= 1 << Index;
|
|
}
|
|
|
|
void markPSInputEnabled(unsigned Index) {
|
|
PSInputEnable |= 1 << Index;
|
|
}
|
|
|
|
bool returnsVoid() const {
|
|
return ReturnsVoid;
|
|
}
|
|
|
|
void setIfReturnsVoid(bool Value) {
|
|
ReturnsVoid = Value;
|
|
}
|
|
|
|
/// \returns A pair of default/requested minimum/maximum flat work group sizes
|
|
/// for this function.
|
|
std::pair<unsigned, unsigned> getFlatWorkGroupSizes() const {
|
|
return FlatWorkGroupSizes;
|
|
}
|
|
|
|
/// \returns Default/requested minimum flat work group size for this function.
|
|
unsigned getMinFlatWorkGroupSize() const {
|
|
return FlatWorkGroupSizes.first;
|
|
}
|
|
|
|
/// \returns Default/requested maximum flat work group size for this function.
|
|
unsigned getMaxFlatWorkGroupSize() const {
|
|
return FlatWorkGroupSizes.second;
|
|
}
|
|
|
|
/// \returns A pair of default/requested minimum/maximum number of waves per
|
|
/// execution unit.
|
|
std::pair<unsigned, unsigned> getWavesPerEU() const {
|
|
return WavesPerEU;
|
|
}
|
|
|
|
/// \returns Default/requested minimum number of waves per execution unit.
|
|
unsigned getMinWavesPerEU() const {
|
|
return WavesPerEU.first;
|
|
}
|
|
|
|
/// \returns Default/requested maximum number of waves per execution unit.
|
|
unsigned getMaxWavesPerEU() const {
|
|
return WavesPerEU.second;
|
|
}
|
|
|
|
/// \returns SGPR used for \p Dim's work group ID.
|
|
unsigned getWorkGroupIDSGPR(unsigned Dim) const {
|
|
switch (Dim) {
|
|
case 0:
|
|
assert(hasWorkGroupIDX());
|
|
return ArgInfo.WorkGroupIDX.getRegister();
|
|
case 1:
|
|
assert(hasWorkGroupIDY());
|
|
return ArgInfo.WorkGroupIDY.getRegister();
|
|
case 2:
|
|
assert(hasWorkGroupIDZ());
|
|
return ArgInfo.WorkGroupIDZ.getRegister();
|
|
}
|
|
llvm_unreachable("unexpected dimension");
|
|
}
|
|
|
|
/// \returns VGPR used for \p Dim' work item ID.
|
|
unsigned getWorkItemIDVGPR(unsigned Dim) const;
|
|
|
|
unsigned getLDSWaveSpillSize() const {
|
|
return LDSWaveSpillSize;
|
|
}
|
|
|
|
const AMDGPUBufferPseudoSourceValue *getBufferPSV(const SIInstrInfo &TII,
|
|
const Value *BufferRsrc) {
|
|
assert(BufferRsrc);
|
|
auto PSV = BufferPSVs.try_emplace(
|
|
BufferRsrc,
|
|
llvm::make_unique<AMDGPUBufferPseudoSourceValue>(TII));
|
|
return PSV.first->second.get();
|
|
}
|
|
|
|
const AMDGPUImagePseudoSourceValue *getImagePSV(const SIInstrInfo &TII,
|
|
const Value *ImgRsrc) {
|
|
assert(ImgRsrc);
|
|
auto PSV = ImagePSVs.try_emplace(
|
|
ImgRsrc,
|
|
llvm::make_unique<AMDGPUImagePseudoSourceValue>(TII));
|
|
return PSV.first->second.get();
|
|
}
|
|
|
|
unsigned getOccupancy() const {
|
|
return Occupancy;
|
|
}
|
|
|
|
unsigned getMinAllowedOccupancy() const {
|
|
if (!isMemoryBound() && !needsWaveLimiter())
|
|
return Occupancy;
|
|
return (Occupancy < 4) ? Occupancy : 4;
|
|
}
|
|
|
|
void limitOccupancy(const MachineFunction &MF);
|
|
|
|
void limitOccupancy(unsigned Limit) {
|
|
if (Occupancy > Limit)
|
|
Occupancy = Limit;
|
|
}
|
|
|
|
void increaseOccupancy(const MachineFunction &MF, unsigned Limit) {
|
|
if (Occupancy < Limit)
|
|
Occupancy = Limit;
|
|
limitOccupancy(MF);
|
|
}
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
|