109 lines
4.2 KiB
C++
109 lines
4.2 KiB
C++
//===-- PPCCallingConv.h - --------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "PPCRegisterInfo.h"
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#include "PPCCallingConv.h"
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#include "PPCSubtarget.h"
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#include "PPCCCState.h"
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using namespace llvm;
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inline bool CC_PPC_AnyReg_Error(unsigned &, MVT &, MVT &,
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CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
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CCState &) {
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llvm_unreachable("The AnyReg calling convention is only supported by the " \
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"stackmap and patchpoint intrinsics.");
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// gracefully fallback to PPC C calling convention on Release builds.
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return false;
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}
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static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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return true;
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}
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static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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static const MCPhysReg ArgRegs[] = {
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10,
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};
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const unsigned NumArgRegs = array_lengthof(ArgRegs);
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unsigned RegNum = State.getFirstUnallocated(ArgRegs);
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// Skip one register if the first unallocated register has an even register
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// number and there are still argument registers available which have not been
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// allocated yet. RegNum is actually an index into ArgRegs, which means we
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// need to skip a register if RegNum is odd.
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if (RegNum != NumArgRegs && RegNum % 2 == 1) {
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State.AllocateReg(ArgRegs[RegNum]);
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}
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// Always return false here, as this function only makes sure that the first
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// unallocated register has an odd register number and does not actually
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// allocate a register for the current argument.
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return false;
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}
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static bool CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(
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unsigned &ValNo, MVT &ValVT, MVT &LocVT, CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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static const MCPhysReg ArgRegs[] = {
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10,
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};
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const unsigned NumArgRegs = array_lengthof(ArgRegs);
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unsigned RegNum = State.getFirstUnallocated(ArgRegs);
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int RegsLeft = NumArgRegs - RegNum;
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// Skip if there is not enough registers left for long double type (4 gpr regs
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// in soft float mode) and put long double argument on the stack.
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if (RegNum != NumArgRegs && RegsLeft < 4) {
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for (int i = 0; i < RegsLeft; i++) {
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State.AllocateReg(ArgRegs[RegNum + i]);
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}
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}
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return false;
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}
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static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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static const MCPhysReg ArgRegs[] = {
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PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8
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};
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const unsigned NumArgRegs = array_lengthof(ArgRegs);
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unsigned RegNum = State.getFirstUnallocated(ArgRegs);
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// If there is only one Floating-point register left we need to put both f64
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// values of a split ppc_fp128 value on the stack.
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if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
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State.AllocateReg(ArgRegs[RegNum]);
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}
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// Always return false here, as this function only makes sure that the two f64
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// values a ppc_fp128 value is split into are both passed in registers or both
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// passed on the stack and does not actually allocate a register for the
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// current argument.
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return false;
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}
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#include "PPCGenCallingConv.inc"
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