794 lines
38 KiB
TableGen
794 lines
38 KiB
TableGen
//===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 x87 FPU instruction set, defining the
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// instructions, and properties of the instructions which are needed for code
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// generation, machine code emission, and analysis.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// FPStack specific DAG Nodes.
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//===----------------------------------------------------------------------===//
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def SDTX86Fld : SDTypeProfile<1, 1, [SDTCisFP<0>,
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SDTCisPtrTy<1>]>;
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def SDTX86Fst : SDTypeProfile<0, 2, [SDTCisFP<0>,
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SDTCisPtrTy<1>]>;
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def SDTX86Fild : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
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def SDTX86Fist : SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisPtrTy<1>]>;
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def SDTX86Fnstsw : SDTypeProfile<1, 1, [SDTCisVT<0, i16>, SDTCisVT<1, i16>]>;
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def SDTX86CwdStore : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
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def X86fld : SDNode<"X86ISD::FLD", SDTX86Fld,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def X86fst : SDNode<"X86ISD::FST", SDTX86Fst,
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[SDNPHasChain, SDNPInGlue, SDNPMayStore,
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SDNPMemOperand]>;
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def X86fild : SDNode<"X86ISD::FILD", SDTX86Fild,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def X86fildflag : SDNode<"X86ISD::FILD_FLAG", SDTX86Fild,
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[SDNPHasChain, SDNPOutGlue, SDNPMayLoad,
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SDNPMemOperand]>;
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def X86fist : SDNode<"X86ISD::FIST", SDTX86Fist,
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[SDNPHasChain, SDNPInGlue, SDNPMayStore,
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SDNPMemOperand]>;
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def X86fp_stsw : SDNode<"X86ISD::FNSTSW16r", SDTX86Fnstsw>;
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def X86fp_to_mem : SDNode<"X86ISD::FP_TO_INT_IN_MEM", SDTX86Fst,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def X86fp_cwd_get16 : SDNode<"X86ISD::FNSTCW16m", SDTX86CwdStore,
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[SDNPHasChain, SDNPMayStore, SDNPSideEffect,
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SDNPMemOperand]>;
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def X86fstf32 : PatFrag<(ops node:$val, node:$ptr),
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(X86fst node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32;
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}]>;
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def X86fstf64 : PatFrag<(ops node:$val, node:$ptr),
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(X86fst node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64;
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}]>;
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def X86fstf80 : PatFrag<(ops node:$val, node:$ptr),
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(X86fst node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80;
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}]>;
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def X86fldf32 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f32;
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}]>;
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def X86fldf64 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f64;
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}]>;
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def X86fldf80 : PatFrag<(ops node:$ptr), (X86fld node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::f80;
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}]>;
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def X86fild16 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def X86fild32 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def X86fild64 : PatFrag<(ops node:$ptr), (X86fild node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def X86fildflag64 : PatFrag<(ops node:$ptr), (X86fildflag node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def X86fist64 : PatFrag<(ops node:$val, node:$ptr),
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(X86fist node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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def X86fp_to_i16mem : PatFrag<(ops node:$val, node:$ptr),
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(X86fp_to_mem node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
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}]>;
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def X86fp_to_i32mem : PatFrag<(ops node:$val, node:$ptr),
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(X86fp_to_mem node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
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}]>;
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def X86fp_to_i64mem : PatFrag<(ops node:$val, node:$ptr),
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(X86fp_to_mem node:$val, node:$ptr), [{
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return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
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}]>;
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//===----------------------------------------------------------------------===//
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// FPStack pattern fragments
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//===----------------------------------------------------------------------===//
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def fpimm0 : FPImmLeaf<fAny, [{
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return Imm.isExactlyValue(+0.0);
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}]>;
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def fpimmneg0 : FPImmLeaf<fAny, [{
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return Imm.isExactlyValue(-0.0);
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}]>;
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def fpimm1 : FPImmLeaf<fAny, [{
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return Imm.isExactlyValue(+1.0);
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}]>;
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def fpimmneg1 : FPImmLeaf<fAny, [{
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return Imm.isExactlyValue(-1.0);
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}]>;
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// Some 'special' instructions - expanded after instruction selection.
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// Clobbers EFLAGS due to OR instruction used internally.
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// FIXME: Can we model this in SelectionDAG?
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let usesCustomInserter = 1, hasNoSchedulingInfo = 1, Defs = [EFLAGS] in {
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def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
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[(X86fp_to_i16mem RFP32:$src, addr:$dst)]>;
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def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
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[(X86fp_to_i32mem RFP32:$src, addr:$dst)]>;
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def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
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[(X86fp_to_i64mem RFP32:$src, addr:$dst)]>;
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def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
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[(X86fp_to_i16mem RFP64:$src, addr:$dst)]>;
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def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
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[(X86fp_to_i32mem RFP64:$src, addr:$dst)]>;
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def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
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[(X86fp_to_i64mem RFP64:$src, addr:$dst)]>;
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def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
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[(X86fp_to_i16mem RFP80:$src, addr:$dst)]>;
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def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
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[(X86fp_to_i32mem RFP80:$src, addr:$dst)]>;
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def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
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[(X86fp_to_i64mem RFP80:$src, addr:$dst)]>;
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}
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// All FP Stack operations are represented with four instructions here. The
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// first three instructions, generated by the instruction selector, use "RFP32"
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// "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
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// 64-bit or 80-bit floating point values. These sizes apply to the values,
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// not the registers, which are always 80 bits; RFP32, RFP64 and RFP80 can be
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// copied to each other without losing information. These instructions are all
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// pseudo instructions and use the "_Fp" suffix.
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// In some cases there are additional variants with a mixture of different
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// register sizes.
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// The second instruction is defined with FPI, which is the actual instruction
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// emitted by the assembler. These use "RST" registers, although frequently
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// the actual register(s) used are implicit. These are always 80 bits.
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// The FP stackifier pass converts one to the other after register allocation
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// occurs.
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//
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// Note that the FpI instruction should have instruction selection info (e.g.
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// a pattern) and the FPI instruction should have emission info (e.g. opcode
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// encoding and asm printing info).
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// FpIf32, FpIf64 - Floating Point Pseudo Instruction template.
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// f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
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// f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
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// f80 instructions cannot use SSE and use neither of these.
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class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32]>;
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class FpIf64<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
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FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64]>;
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// Factoring for arithmetic.
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multiclass FPBinary_rr<SDNode OpNode> {
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// Register op register -> register
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// These are separated out because they have no reversed form.
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def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
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[(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
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def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
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[(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
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def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
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[(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
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}
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// The FopST0 series are not included here because of the irregularities
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// in where the 'r' goes in assembly output.
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// These instructions cannot address 80-bit memory.
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multiclass FPBinary<SDNode OpNode, Format fp, string asmstring,
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bit Forward = 1> {
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// ST(0) = ST(0) + [mem]
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def _Fp32m : FpIf32<(outs RFP32:$dst),
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(ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
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[!if(Forward,
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(set RFP32:$dst,
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(OpNode RFP32:$src1, (loadf32 addr:$src2))),
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(set RFP32:$dst,
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(OpNode (loadf32 addr:$src2), RFP32:$src1)))]>;
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def _Fp64m : FpIf64<(outs RFP64:$dst),
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(ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
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[!if(Forward,
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(set RFP64:$dst,
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(OpNode RFP64:$src1, (loadf64 addr:$src2))),
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(set RFP64:$dst,
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(OpNode (loadf64 addr:$src2), RFP64:$src1)))]>;
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def _Fp64m32: FpIf64<(outs RFP64:$dst),
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(ins RFP64:$src1, f32mem:$src2), OneArgFPRW,
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[!if(Forward,
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(set RFP64:$dst,
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(OpNode RFP64:$src1, (f64 (extloadf32 addr:$src2)))),
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(set RFP64:$dst,
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(OpNode (f64 (extloadf32 addr:$src2)), RFP64:$src1)))]>;
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def _Fp80m32: FpI_<(outs RFP80:$dst),
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(ins RFP80:$src1, f32mem:$src2), OneArgFPRW,
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[!if(Forward,
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(set RFP80:$dst,
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(OpNode RFP80:$src1, (f80 (extloadf32 addr:$src2)))),
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(set RFP80:$dst,
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(OpNode (f80 (extloadf32 addr:$src2)), RFP80:$src1)))]>;
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def _Fp80m64: FpI_<(outs RFP80:$dst),
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(ins RFP80:$src1, f64mem:$src2), OneArgFPRW,
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[!if(Forward,
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(set RFP80:$dst,
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(OpNode RFP80:$src1, (f80 (extloadf64 addr:$src2)))),
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(set RFP80:$dst,
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(OpNode (f80 (extloadf64 addr:$src2)), RFP80:$src1)))]>;
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let mayLoad = 1 in
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def _F32m : FPI<0xD8, fp, (outs), (ins f32mem:$src),
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!strconcat("f", asmstring, "{s}\t$src")>;
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let mayLoad = 1 in
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def _F64m : FPI<0xDC, fp, (outs), (ins f64mem:$src),
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!strconcat("f", asmstring, "{l}\t$src")>;
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// ST(0) = ST(0) + [memint]
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def _FpI16m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i16mem:$src2),
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OneArgFPRW,
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[!if(Forward,
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(set RFP32:$dst,
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(OpNode RFP32:$src1, (X86fild16 addr:$src2))),
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(set RFP32:$dst,
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(OpNode (X86fild16 addr:$src2), RFP32:$src1)))]>;
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def _FpI32m32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, i32mem:$src2),
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OneArgFPRW,
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[!if(Forward,
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(set RFP32:$dst,
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(OpNode RFP32:$src1, (X86fild32 addr:$src2))),
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(set RFP32:$dst,
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(OpNode (X86fild32 addr:$src2), RFP32:$src1)))]>;
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def _FpI16m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i16mem:$src2),
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OneArgFPRW,
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[!if(Forward,
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(set RFP64:$dst,
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(OpNode RFP64:$src1, (X86fild16 addr:$src2))),
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(set RFP64:$dst,
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(OpNode (X86fild16 addr:$src2), RFP64:$src1)))]>;
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def _FpI32m64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, i32mem:$src2),
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OneArgFPRW,
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[!if(Forward,
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(set RFP64:$dst,
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(OpNode RFP64:$src1, (X86fild32 addr:$src2))),
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(set RFP64:$dst,
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(OpNode (X86fild32 addr:$src2), RFP64:$src1)))]>;
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def _FpI16m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i16mem:$src2),
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OneArgFPRW,
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[!if(Forward,
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(set RFP80:$dst,
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(OpNode RFP80:$src1, (X86fild16 addr:$src2))),
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(set RFP80:$dst,
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(OpNode (X86fild16 addr:$src2), RFP80:$src1)))]>;
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def _FpI32m80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, i32mem:$src2),
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OneArgFPRW,
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[!if(Forward,
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(set RFP80:$dst,
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(OpNode RFP80:$src1, (X86fild32 addr:$src2))),
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(set RFP80:$dst,
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(OpNode (X86fild32 addr:$src2), RFP80:$src1)))]>;
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let mayLoad = 1 in
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def _FI16m : FPI<0xDE, fp, (outs), (ins i16mem:$src),
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!strconcat("fi", asmstring, "{s}\t$src")>;
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let mayLoad = 1 in
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def _FI32m : FPI<0xDA, fp, (outs), (ins i32mem:$src),
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!strconcat("fi", asmstring, "{l}\t$src")>;
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}
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let Defs = [FPSW], Uses = [FPCW] in {
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// FPBinary_rr just defines pseudo-instructions, no need to set a scheduling
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// resources.
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let hasNoSchedulingInfo = 1 in {
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defm ADD : FPBinary_rr<fadd>;
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defm SUB : FPBinary_rr<fsub>;
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defm MUL : FPBinary_rr<fmul>;
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defm DIV : FPBinary_rr<fdiv>;
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}
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// Sets the scheduling resources for the actual NAME#_F<size>m defintions.
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let SchedRW = [WriteFAddLd] in {
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defm ADD : FPBinary<fadd, MRM0m, "add">;
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defm SUB : FPBinary<fsub, MRM4m, "sub">;
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defm SUBR: FPBinary<fsub ,MRM5m, "subr", 0>;
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}
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let SchedRW = [WriteFMulLd] in {
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defm MUL : FPBinary<fmul, MRM1m, "mul">;
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}
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let SchedRW = [WriteFDivLd] in {
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defm DIV : FPBinary<fdiv, MRM6m, "div">;
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defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>;
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}
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} // Defs = [FPSW]
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class FPST0rInst<Format fp, string asm>
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: FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>;
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class FPrST0Inst<Format fp, string asm>
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: FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>;
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class FPrST0PInst<Format fp, string asm>
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: FPI<0xDE, fp, (outs), (ins RSTi:$op), asm>;
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// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
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// of some of the 'reverse' forms of the fsub and fdiv instructions. As such,
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// we have to put some 'r's in and take them out of weird places.
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let SchedRW = [WriteFAdd], Defs = [FPSW], Uses = [FPCW] in {
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def ADD_FST0r : FPST0rInst <MRM0r, "fadd\t{$op, %st|st, $op}">;
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def ADD_FrST0 : FPrST0Inst <MRM0r, "fadd\t{%st, $op|$op, st}">;
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def ADD_FPrST0 : FPrST0PInst<MRM0r, "faddp\t{%st, $op|$op, st}">;
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def SUBR_FST0r : FPST0rInst <MRM5r, "fsubr\t{$op, %st|st, $op}">;
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def SUB_FrST0 : FPrST0Inst <MRM5r, "fsub{r}\t{%st, $op|$op, st}">;
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def SUB_FPrST0 : FPrST0PInst<MRM5r, "fsub{r}p\t{%st, $op|$op, st}">;
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def SUB_FST0r : FPST0rInst <MRM4r, "fsub\t{$op, %st|st, $op}">;
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def SUBR_FrST0 : FPrST0Inst <MRM4r, "fsub{|r}\t{%st, $op|$op, st}">;
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def SUBR_FPrST0 : FPrST0PInst<MRM4r, "fsub{|r}p\t{%st, $op|$op, st}">;
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} // SchedRW
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let SchedRW = [WriteFCom], Defs = [FPSW], Uses = [FPCW] in {
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def COM_FST0r : FPST0rInst <MRM2r, "fcom\t$op">;
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def COMP_FST0r : FPST0rInst <MRM3r, "fcomp\t$op">;
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} // SchedRW
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let SchedRW = [WriteFMul], Defs = [FPSW], Uses = [FPCW] in {
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def MUL_FST0r : FPST0rInst <MRM1r, "fmul\t{$op, %st|st, $op}">;
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def MUL_FrST0 : FPrST0Inst <MRM1r, "fmul\t{%st, $op|$op, st}">;
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def MUL_FPrST0 : FPrST0PInst<MRM1r, "fmulp\t{%st, $op|$op, st}">;
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} // SchedRW
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let SchedRW = [WriteFDiv], Defs = [FPSW], Uses = [FPCW] in {
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|
def DIVR_FST0r : FPST0rInst <MRM7r, "fdivr\t{$op, %st|st, $op}">;
|
|
def DIV_FrST0 : FPrST0Inst <MRM7r, "fdiv{r}\t{%st, $op|$op, st}">;
|
|
def DIV_FPrST0 : FPrST0PInst<MRM7r, "fdiv{r}p\t{%st, $op|$op, st}">;
|
|
def DIV_FST0r : FPST0rInst <MRM6r, "fdiv\t{$op, %st|st, $op}">;
|
|
def DIVR_FrST0 : FPrST0Inst <MRM6r, "fdiv{|r}\t{%st, $op|$op, st}">;
|
|
def DIVR_FPrST0 : FPrST0PInst<MRM6r, "fdiv{|r}p\t{%st, $op|$op, st}">;
|
|
} // SchedRW
|
|
|
|
// Unary operations.
|
|
multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> {
|
|
def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
|
|
[(set RFP32:$dst, (OpNode RFP32:$src))]>;
|
|
def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
|
|
[(set RFP64:$dst, (OpNode RFP64:$src))]>;
|
|
def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
|
|
[(set RFP80:$dst, (OpNode RFP80:$src))]>;
|
|
def _F : FPI<0xD9, fp, (outs), (ins), asmstring>;
|
|
}
|
|
|
|
let Defs = [FPSW], Uses = [FPCW] in {
|
|
|
|
let SchedRW = [WriteFSign] in {
|
|
defm CHS : FPUnary<fneg, MRM_E0, "fchs">;
|
|
defm ABS : FPUnary<fabs, MRM_E1, "fabs">;
|
|
}
|
|
|
|
let SchedRW = [WriteFSqrt80] in
|
|
defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">;
|
|
|
|
let SchedRW = [WriteMicrocoded] in {
|
|
defm SIN : FPUnary<fsin, MRM_FE, "fsin">;
|
|
defm COS : FPUnary<fcos, MRM_FF, "fcos">;
|
|
}
|
|
|
|
let SchedRW = [WriteFCom] in {
|
|
let hasSideEffects = 0 in {
|
|
def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
|
|
def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
|
|
def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
|
|
} // hasSideEffects
|
|
|
|
def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;
|
|
} // SchedRW
|
|
} // Defs = [FPSW]
|
|
|
|
// Versions of FP instructions that take a single memory operand. Added for the
|
|
// disassembler; remove as they are included with patterns elsewhere.
|
|
let SchedRW = [WriteFComLd], Defs = [FPSW], Uses = [FPCW] in {
|
|
def FCOM32m : FPI<0xD8, MRM2m, (outs), (ins f32mem:$src), "fcom{s}\t$src">;
|
|
def FCOMP32m : FPI<0xD8, MRM3m, (outs), (ins f32mem:$src), "fcomp{s}\t$src">;
|
|
|
|
def FCOM64m : FPI<0xDC, MRM2m, (outs), (ins f64mem:$src), "fcom{l}\t$src">;
|
|
def FCOMP64m : FPI<0xDC, MRM3m, (outs), (ins f64mem:$src), "fcomp{l}\t$src">;
|
|
|
|
def FICOM16m : FPI<0xDE, MRM2m, (outs), (ins i16mem:$src), "ficom{s}\t$src">;
|
|
def FICOMP16m: FPI<0xDE, MRM3m, (outs), (ins i16mem:$src), "ficomp{s}\t$src">;
|
|
|
|
def FICOM32m : FPI<0xDA, MRM2m, (outs), (ins i32mem:$src), "ficom{l}\t$src">;
|
|
def FICOMP32m: FPI<0xDA, MRM3m, (outs), (ins i32mem:$src), "ficomp{l}\t$src">;
|
|
} // SchedRW
|
|
|
|
let SchedRW = [WriteMicrocoded] in {
|
|
def FLDENVm : FPI<0xD9, MRM4m, (outs), (ins f32mem:$src), "fldenv\t$src">;
|
|
def FSTENVm : FPI<0xD9, MRM6m, (outs), (ins f32mem:$dst), "fnstenv\t$dst">;
|
|
|
|
def FRSTORm : FPI<0xDD, MRM4m, (outs), (ins f32mem:$dst), "frstor\t$dst">;
|
|
def FSAVEm : FPI<0xDD, MRM6m, (outs), (ins f32mem:$dst), "fnsave\t$dst">;
|
|
def FNSTSWm : FPI<0xDD, MRM7m, (outs), (ins i16mem:$dst), "fnstsw\t$dst">;
|
|
|
|
def FBLDm : FPI<0xDF, MRM4m, (outs), (ins f80mem:$src), "fbld\t$src">;
|
|
def FBSTPm : FPI<0xDF, MRM6m, (outs), (ins f80mem:$dst), "fbstp\t$dst">;
|
|
} // SchedRW
|
|
|
|
// Floating point cmovs.
|
|
class FpIf32CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
|
|
FpI_<outs, ins, fp, pattern>, Requires<[FPStackf32, HasCMov]>;
|
|
class FpIf64CMov<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
|
|
FpI_<outs, ins, fp, pattern>, Requires<[FPStackf64, HasCMov]>;
|
|
|
|
multiclass FPCMov<PatLeaf cc> {
|
|
def _Fp32 : FpIf32CMov<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2),
|
|
CondMovFP,
|
|
[(set RFP32:$dst, (X86cmov RFP32:$src1, RFP32:$src2,
|
|
cc, EFLAGS))]>;
|
|
def _Fp64 : FpIf64CMov<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2),
|
|
CondMovFP,
|
|
[(set RFP64:$dst, (X86cmov RFP64:$src1, RFP64:$src2,
|
|
cc, EFLAGS))]>;
|
|
def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2),
|
|
CondMovFP,
|
|
[(set RFP80:$dst, (X86cmov RFP80:$src1, RFP80:$src2,
|
|
cc, EFLAGS))]>,
|
|
Requires<[HasCMov]>;
|
|
}
|
|
|
|
let Defs = [FPSW] in {
|
|
let SchedRW = [WriteFCMOV] in {
|
|
let Uses = [EFLAGS], Constraints = "$src1 = $dst" in {
|
|
defm CMOVB : FPCMov<X86_COND_B>;
|
|
defm CMOVBE : FPCMov<X86_COND_BE>;
|
|
defm CMOVE : FPCMov<X86_COND_E>;
|
|
defm CMOVP : FPCMov<X86_COND_P>;
|
|
defm CMOVNB : FPCMov<X86_COND_AE>;
|
|
defm CMOVNBE: FPCMov<X86_COND_A>;
|
|
defm CMOVNE : FPCMov<X86_COND_NE>;
|
|
defm CMOVNP : FPCMov<X86_COND_NP>;
|
|
} // Uses = [EFLAGS], Constraints = "$src1 = $dst"
|
|
|
|
let Predicates = [HasCMov] in {
|
|
// These are not factored because there's no clean way to pass DA/DB.
|
|
def CMOVB_F : FPI<0xDA, MRM0r, (outs), (ins RSTi:$op),
|
|
"fcmovb\t{$op, %st|st, $op}">;
|
|
def CMOVBE_F : FPI<0xDA, MRM2r, (outs), (ins RSTi:$op),
|
|
"fcmovbe\t{$op, %st|st, $op}">;
|
|
def CMOVE_F : FPI<0xDA, MRM1r, (outs), (ins RSTi:$op),
|
|
"fcmove\t{$op, %st|st, $op}">;
|
|
def CMOVP_F : FPI<0xDA, MRM3r, (outs), (ins RSTi:$op),
|
|
"fcmovu\t{$op, %st|st, $op}">;
|
|
def CMOVNB_F : FPI<0xDB, MRM0r, (outs), (ins RSTi:$op),
|
|
"fcmovnb\t{$op, %st|st, $op}">;
|
|
def CMOVNBE_F: FPI<0xDB, MRM2r, (outs), (ins RSTi:$op),
|
|
"fcmovnbe\t{$op, %st|st, $op}">;
|
|
def CMOVNE_F : FPI<0xDB, MRM1r, (outs), (ins RSTi:$op),
|
|
"fcmovne\t{$op, %st|st, $op}">;
|
|
def CMOVNP_F : FPI<0xDB, MRM3r, (outs), (ins RSTi:$op),
|
|
"fcmovnu\t{$op, %st|st, $op}">;
|
|
} // Predicates = [HasCMov]
|
|
} // SchedRW
|
|
|
|
// Floating point loads & stores.
|
|
let SchedRW = [WriteLoad], Uses = [FPCW] in {
|
|
let canFoldAsLoad = 1 in {
|
|
def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
|
|
[(set RFP32:$dst, (loadf32 addr:$src))]>;
|
|
def LD_Fp64m : FpIf64<(outs RFP64:$dst), (ins f64mem:$src), ZeroArgFP,
|
|
[(set RFP64:$dst, (loadf64 addr:$src))]>;
|
|
def LD_Fp80m : FpI_<(outs RFP80:$dst), (ins f80mem:$src), ZeroArgFP,
|
|
[(set RFP80:$dst, (loadf80 addr:$src))]>;
|
|
} // canFoldAsLoad
|
|
def LD_Fp32m64 : FpIf64<(outs RFP64:$dst), (ins f32mem:$src), ZeroArgFP,
|
|
[(set RFP64:$dst, (f64 (extloadf32 addr:$src)))]>;
|
|
def LD_Fp64m80 : FpI_<(outs RFP80:$dst), (ins f64mem:$src), ZeroArgFP,
|
|
[(set RFP80:$dst, (f80 (extloadf64 addr:$src)))]>;
|
|
def LD_Fp32m80 : FpI_<(outs RFP80:$dst), (ins f32mem:$src), ZeroArgFP,
|
|
[(set RFP80:$dst, (f80 (extloadf32 addr:$src)))]>;
|
|
def ILD_Fp16m32: FpIf32<(outs RFP32:$dst), (ins i16mem:$src), ZeroArgFP,
|
|
[(set RFP32:$dst, (X86fild16 addr:$src))]>;
|
|
def ILD_Fp32m32: FpIf32<(outs RFP32:$dst), (ins i32mem:$src), ZeroArgFP,
|
|
[(set RFP32:$dst, (X86fild32 addr:$src))]>;
|
|
def ILD_Fp64m32: FpIf32<(outs RFP32:$dst), (ins i64mem:$src), ZeroArgFP,
|
|
[(set RFP32:$dst, (X86fild64 addr:$src))]>;
|
|
def ILD_Fp16m64: FpIf64<(outs RFP64:$dst), (ins i16mem:$src), ZeroArgFP,
|
|
[(set RFP64:$dst, (X86fild16 addr:$src))]>;
|
|
def ILD_Fp32m64: FpIf64<(outs RFP64:$dst), (ins i32mem:$src), ZeroArgFP,
|
|
[(set RFP64:$dst, (X86fild32 addr:$src))]>;
|
|
def ILD_Fp64m64: FpIf64<(outs RFP64:$dst), (ins i64mem:$src), ZeroArgFP,
|
|
[(set RFP64:$dst, (X86fild64 addr:$src))]>;
|
|
def ILD_Fp16m80: FpI_<(outs RFP80:$dst), (ins i16mem:$src), ZeroArgFP,
|
|
[(set RFP80:$dst, (X86fild16 addr:$src))]>;
|
|
def ILD_Fp32m80: FpI_<(outs RFP80:$dst), (ins i32mem:$src), ZeroArgFP,
|
|
[(set RFP80:$dst, (X86fild32 addr:$src))]>;
|
|
def ILD_Fp64m80: FpI_<(outs RFP80:$dst), (ins i64mem:$src), ZeroArgFP,
|
|
[(set RFP80:$dst, (X86fild64 addr:$src))]>;
|
|
} // SchedRW
|
|
|
|
let SchedRW = [WriteStore], Uses = [FPCW] in {
|
|
def ST_Fp32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP,
|
|
[(store RFP32:$src, addr:$op)]>;
|
|
def ST_Fp64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP,
|
|
[(truncstoref32 RFP64:$src, addr:$op)]>;
|
|
def ST_Fp64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP,
|
|
[(store RFP64:$src, addr:$op)]>;
|
|
def ST_Fp80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP,
|
|
[(truncstoref32 RFP80:$src, addr:$op)]>;
|
|
def ST_Fp80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP,
|
|
[(truncstoref64 RFP80:$src, addr:$op)]>;
|
|
// FST does not support 80-bit memory target; FSTP must be used.
|
|
|
|
let mayStore = 1, hasSideEffects = 0 in {
|
|
def ST_FpP32m : FpIf32<(outs), (ins f32mem:$op, RFP32:$src), OneArgFP, []>;
|
|
def ST_FpP64m32 : FpIf64<(outs), (ins f32mem:$op, RFP64:$src), OneArgFP, []>;
|
|
def ST_FpP64m : FpIf64<(outs), (ins f64mem:$op, RFP64:$src), OneArgFP, []>;
|
|
def ST_FpP80m32 : FpI_<(outs), (ins f32mem:$op, RFP80:$src), OneArgFP, []>;
|
|
def ST_FpP80m64 : FpI_<(outs), (ins f64mem:$op, RFP80:$src), OneArgFP, []>;
|
|
} // mayStore
|
|
|
|
def ST_FpP80m : FpI_<(outs), (ins f80mem:$op, RFP80:$src), OneArgFP,
|
|
[(store RFP80:$src, addr:$op)]>;
|
|
|
|
let mayStore = 1, hasSideEffects = 0 in {
|
|
def IST_Fp16m32 : FpIf32<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP, []>;
|
|
def IST_Fp32m32 : FpIf32<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP, []>;
|
|
def IST_Fp64m32 : FpIf32<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP, []>;
|
|
def IST_Fp16m64 : FpIf64<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP, []>;
|
|
def IST_Fp32m64 : FpIf64<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP, []>;
|
|
def IST_Fp64m64 : FpIf64<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP, []>;
|
|
def IST_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP, []>;
|
|
def IST_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP, []>;
|
|
def IST_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP, []>;
|
|
} // mayStore
|
|
} // SchedRW, Uses = [FPCW]
|
|
|
|
let mayLoad = 1, SchedRW = [WriteLoad], Uses = [FPCW] in {
|
|
def LD_F32m : FPI<0xD9, MRM0m, (outs), (ins f32mem:$src), "fld{s}\t$src">;
|
|
def LD_F64m : FPI<0xDD, MRM0m, (outs), (ins f64mem:$src), "fld{l}\t$src">;
|
|
def LD_F80m : FPI<0xDB, MRM5m, (outs), (ins f80mem:$src), "fld{t}\t$src">;
|
|
def ILD_F16m : FPI<0xDF, MRM0m, (outs), (ins i16mem:$src), "fild{s}\t$src">;
|
|
def ILD_F32m : FPI<0xDB, MRM0m, (outs), (ins i32mem:$src), "fild{l}\t$src">;
|
|
def ILD_F64m : FPI<0xDF, MRM5m, (outs), (ins i64mem:$src), "fild{ll}\t$src">;
|
|
}
|
|
let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {
|
|
def ST_F32m : FPI<0xD9, MRM2m, (outs), (ins f32mem:$dst), "fst{s}\t$dst">;
|
|
def ST_F64m : FPI<0xDD, MRM2m, (outs), (ins f64mem:$dst), "fst{l}\t$dst">;
|
|
def ST_FP32m : FPI<0xD9, MRM3m, (outs), (ins f32mem:$dst), "fstp{s}\t$dst">;
|
|
def ST_FP64m : FPI<0xDD, MRM3m, (outs), (ins f64mem:$dst), "fstp{l}\t$dst">;
|
|
def ST_FP80m : FPI<0xDB, MRM7m, (outs), (ins f80mem:$dst), "fstp{t}\t$dst">;
|
|
def IST_F16m : FPI<0xDF, MRM2m, (outs), (ins i16mem:$dst), "fist{s}\t$dst">;
|
|
def IST_F32m : FPI<0xDB, MRM2m, (outs), (ins i32mem:$dst), "fist{l}\t$dst">;
|
|
def IST_FP16m : FPI<0xDF, MRM3m, (outs), (ins i16mem:$dst), "fistp{s}\t$dst">;
|
|
def IST_FP32m : FPI<0xDB, MRM3m, (outs), (ins i32mem:$dst), "fistp{l}\t$dst">;
|
|
def IST_FP64m : FPI<0xDF, MRM7m, (outs), (ins i64mem:$dst), "fistp{ll}\t$dst">;
|
|
}
|
|
|
|
// FISTTP requires SSE3 even though it's a FPStack op.
|
|
let Predicates = [HasSSE3], SchedRW = [WriteStore], Uses = [FPCW] in {
|
|
def ISTT_Fp16m32 : FpI_<(outs), (ins i16mem:$op, RFP32:$src), OneArgFP,
|
|
[(X86fp_to_i16mem RFP32:$src, addr:$op)]>;
|
|
def ISTT_Fp32m32 : FpI_<(outs), (ins i32mem:$op, RFP32:$src), OneArgFP,
|
|
[(X86fp_to_i32mem RFP32:$src, addr:$op)]>;
|
|
def ISTT_Fp64m32 : FpI_<(outs), (ins i64mem:$op, RFP32:$src), OneArgFP,
|
|
[(X86fp_to_i64mem RFP32:$src, addr:$op)]>;
|
|
def ISTT_Fp16m64 : FpI_<(outs), (ins i16mem:$op, RFP64:$src), OneArgFP,
|
|
[(X86fp_to_i16mem RFP64:$src, addr:$op)]>;
|
|
def ISTT_Fp32m64 : FpI_<(outs), (ins i32mem:$op, RFP64:$src), OneArgFP,
|
|
[(X86fp_to_i32mem RFP64:$src, addr:$op)]>;
|
|
def ISTT_Fp64m64 : FpI_<(outs), (ins i64mem:$op, RFP64:$src), OneArgFP,
|
|
[(X86fp_to_i64mem RFP64:$src, addr:$op)]>;
|
|
def ISTT_Fp16m80 : FpI_<(outs), (ins i16mem:$op, RFP80:$src), OneArgFP,
|
|
[(X86fp_to_i16mem RFP80:$src, addr:$op)]>;
|
|
def ISTT_Fp32m80 : FpI_<(outs), (ins i32mem:$op, RFP80:$src), OneArgFP,
|
|
[(X86fp_to_i32mem RFP80:$src, addr:$op)]>;
|
|
def ISTT_Fp64m80 : FpI_<(outs), (ins i64mem:$op, RFP80:$src), OneArgFP,
|
|
[(X86fp_to_i64mem RFP80:$src, addr:$op)]>;
|
|
} // Predicates = [HasSSE3]
|
|
|
|
let mayStore = 1, SchedRW = [WriteStore], Uses = [FPCW] in {
|
|
def ISTT_FP16m : FPI<0xDF, MRM1m, (outs), (ins i16mem:$dst), "fisttp{s}\t$dst">;
|
|
def ISTT_FP32m : FPI<0xDB, MRM1m, (outs), (ins i32mem:$dst), "fisttp{l}\t$dst">;
|
|
def ISTT_FP64m : FPI<0xDD, MRM1m, (outs), (ins i64mem:$dst), "fisttp{ll}\t$dst">;
|
|
}
|
|
|
|
// FP Stack manipulation instructions.
|
|
let SchedRW = [WriteMove], Uses = [FPCW] in {
|
|
def LD_Frr : FPI<0xD9, MRM0r, (outs), (ins RSTi:$op), "fld\t$op">;
|
|
def ST_Frr : FPI<0xDD, MRM2r, (outs), (ins RSTi:$op), "fst\t$op">;
|
|
def ST_FPrr : FPI<0xDD, MRM3r, (outs), (ins RSTi:$op), "fstp\t$op">;
|
|
def XCH_F : FPI<0xD9, MRM1r, (outs), (ins RSTi:$op), "fxch\t$op">;
|
|
}
|
|
|
|
// Floating point constant loads.
|
|
let SchedRW = [WriteZero], Uses = [FPCW] in {
|
|
def LD_Fp032 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
|
|
[(set RFP32:$dst, fpimm0)]>;
|
|
def LD_Fp132 : FpIf32<(outs RFP32:$dst), (ins), ZeroArgFP,
|
|
[(set RFP32:$dst, fpimm1)]>;
|
|
def LD_Fp064 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
|
|
[(set RFP64:$dst, fpimm0)]>;
|
|
def LD_Fp164 : FpIf64<(outs RFP64:$dst), (ins), ZeroArgFP,
|
|
[(set RFP64:$dst, fpimm1)]>;
|
|
def LD_Fp080 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
|
|
[(set RFP80:$dst, fpimm0)]>;
|
|
def LD_Fp180 : FpI_<(outs RFP80:$dst), (ins), ZeroArgFP,
|
|
[(set RFP80:$dst, fpimm1)]>;
|
|
}
|
|
|
|
let SchedRW = [WriteFLD0], Uses = [FPCW] in
|
|
def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz">;
|
|
|
|
let SchedRW = [WriteFLD1], Uses = [FPCW] in
|
|
def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1">;
|
|
|
|
let SchedRW = [WriteFLDC], Uses = [FPCW] in {
|
|
def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", []>;
|
|
def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", []>;
|
|
def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", []>;
|
|
def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", []>;
|
|
def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", []>;
|
|
} // SchedRW
|
|
|
|
// Floating point compares.
|
|
let SchedRW = [WriteFCom], Uses = [FPCW] in {
|
|
def UCOM_Fpr32 : FpIf32<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
|
[(set FPSW, (trunc (X86cmp RFP32:$lhs, RFP32:$rhs)))]>;
|
|
def UCOM_Fpr64 : FpIf64<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
|
[(set FPSW, (trunc (X86cmp RFP64:$lhs, RFP64:$rhs)))]>;
|
|
def UCOM_Fpr80 : FpI_ <(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
|
[(set FPSW, (trunc (X86cmp RFP80:$lhs, RFP80:$rhs)))]>;
|
|
} // SchedRW
|
|
} // Defs = [FPSW]
|
|
|
|
let SchedRW = [WriteFCom] in {
|
|
// CC = ST(0) cmp ST(i)
|
|
let Defs = [EFLAGS, FPSW], Uses = [FPCW] in {
|
|
def UCOM_FpIr32: FpI_<(outs), (ins RFP32:$lhs, RFP32:$rhs), CompareFP,
|
|
[(set EFLAGS, (X86cmp RFP32:$lhs, RFP32:$rhs))]>,
|
|
Requires<[FPStackf32, HasCMov]>;
|
|
def UCOM_FpIr64: FpI_<(outs), (ins RFP64:$lhs, RFP64:$rhs), CompareFP,
|
|
[(set EFLAGS, (X86cmp RFP64:$lhs, RFP64:$rhs))]>,
|
|
Requires<[FPStackf64, HasCMov]>;
|
|
def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
|
|
[(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>,
|
|
Requires<[HasCMov]>;
|
|
}
|
|
|
|
let Defs = [FPSW], Uses = [ST0, FPCW] in {
|
|
def UCOM_Fr : FPI<0xDD, MRM4r, // FPSW = cmp ST(0) with ST(i)
|
|
(outs), (ins RSTi:$reg), "fucom\t$reg">;
|
|
def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
|
|
(outs), (ins RSTi:$reg), "fucomp\t$reg">;
|
|
def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop
|
|
(outs), (ins), "fucompp">;
|
|
}
|
|
|
|
let Defs = [EFLAGS, FPSW], Uses = [ST0, FPCW] in {
|
|
def UCOM_FIr : FPI<0xDB, MRM5r, // CC = cmp ST(0) with ST(i)
|
|
(outs), (ins RSTi:$reg), "fucomi\t{$reg, %st|st, $reg}">;
|
|
def UCOM_FIPr : FPI<0xDF, MRM5r, // CC = cmp ST(0) with ST(i), pop
|
|
(outs), (ins RSTi:$reg), "fucompi\t{$reg, %st|st, $reg}">;
|
|
|
|
def COM_FIr : FPI<0xDB, MRM6r, (outs), (ins RSTi:$reg),
|
|
"fcomi\t{$reg, %st|st, $reg}">;
|
|
def COM_FIPr : FPI<0xDF, MRM6r, (outs), (ins RSTi:$reg),
|
|
"fcompi\t{$reg, %st|st, $reg}">;
|
|
}
|
|
} // SchedRW
|
|
|
|
// Floating point flag ops.
|
|
let SchedRW = [WriteALU] in {
|
|
let Defs = [AX], Uses = [FPSW] in
|
|
def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags
|
|
(outs), (ins), "fnstsw\t{%ax|ax}",
|
|
[(set AX, (X86fp_stsw FPSW))]>;
|
|
let Defs = [FPSW], Uses = [FPCW] in
|
|
def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
|
|
(outs), (ins i16mem:$dst), "fnstcw\t$dst",
|
|
[(X86fp_cwd_get16 addr:$dst)]>;
|
|
} // SchedRW
|
|
let Defs = [FPSW,FPCW], mayLoad = 1 in
|
|
def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
|
|
(outs), (ins i16mem:$dst), "fldcw\t$dst", []>,
|
|
Sched<[WriteLoad]>;
|
|
|
|
// FPU control instructions
|
|
let SchedRW = [WriteMicrocoded] in {
|
|
let Defs = [FPSW] in {
|
|
def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", []>;
|
|
def FFREE : FPI<0xDD, MRM0r, (outs), (ins RSTi:$reg), "ffree\t$reg">;
|
|
def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RSTi:$reg), "ffreep\t$reg">;
|
|
|
|
// Clear exceptions
|
|
def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", []>;
|
|
} // Defs = [FPSW]
|
|
} // SchedRW
|
|
|
|
// Operand-less floating-point instructions for the disassembler.
|
|
def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", []>, Sched<[WriteNop]>;
|
|
|
|
let SchedRW = [WriteMicrocoded] in {
|
|
let Defs = [FPSW] in {
|
|
def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
|
|
def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", []>;
|
|
def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", []>;
|
|
def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", []>;
|
|
def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", []>;
|
|
def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", []>;
|
|
def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", []>;
|
|
def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", []>;
|
|
def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", []>;
|
|
def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", []>;
|
|
def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", []>;
|
|
def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", []>;
|
|
def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", []>;
|
|
def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", []>;
|
|
def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", []>;
|
|
def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", []>;
|
|
} // Defs = [FPSW]
|
|
|
|
def FXSAVE : I<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
|
|
"fxsave\t$dst", [(int_x86_fxsave addr:$dst)]>, TB,
|
|
Requires<[HasFXSR]>;
|
|
def FXSAVE64 : RI<0xAE, MRM0m, (outs), (ins opaquemem:$dst),
|
|
"fxsave64\t$dst", [(int_x86_fxsave64 addr:$dst)]>,
|
|
TB, Requires<[HasFXSR, In64BitMode]>;
|
|
def FXRSTOR : I<0xAE, MRM1m, (outs), (ins opaquemem:$src),
|
|
"fxrstor\t$src", [(int_x86_fxrstor addr:$src)]>,
|
|
TB, Requires<[HasFXSR]>;
|
|
def FXRSTOR64 : RI<0xAE, MRM1m, (outs), (ins opaquemem:$src),
|
|
"fxrstor64\t$src", [(int_x86_fxrstor64 addr:$src)]>,
|
|
TB, Requires<[HasFXSR, In64BitMode]>;
|
|
} // SchedRW
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Required for RET of f32 / f64 / f80 values.
|
|
def : Pat<(X86fldf32 addr:$src), (LD_Fp32m addr:$src)>;
|
|
def : Pat<(X86fldf64 addr:$src), (LD_Fp64m addr:$src)>;
|
|
def : Pat<(X86fldf80 addr:$src), (LD_Fp80m addr:$src)>;
|
|
|
|
// Required for CALL which return f32 / f64 / f80 values.
|
|
def : Pat<(X86fstf32 RFP32:$src, addr:$op), (ST_Fp32m addr:$op, RFP32:$src)>;
|
|
def : Pat<(X86fstf32 RFP64:$src, addr:$op), (ST_Fp64m32 addr:$op, RFP64:$src)>;
|
|
def : Pat<(X86fstf64 RFP64:$src, addr:$op), (ST_Fp64m addr:$op, RFP64:$src)>;
|
|
def : Pat<(X86fstf32 RFP80:$src, addr:$op), (ST_Fp80m32 addr:$op, RFP80:$src)>;
|
|
def : Pat<(X86fstf64 RFP80:$src, addr:$op), (ST_Fp80m64 addr:$op, RFP80:$src)>;
|
|
def : Pat<(X86fstf80 RFP80:$src, addr:$op), (ST_FpP80m addr:$op, RFP80:$src)>;
|
|
|
|
// Floating point constant -0.0 and -1.0
|
|
def : Pat<(f32 fpimmneg0), (CHS_Fp32 (LD_Fp032))>, Requires<[FPStackf32]>;
|
|
def : Pat<(f32 fpimmneg1), (CHS_Fp32 (LD_Fp132))>, Requires<[FPStackf32]>;
|
|
def : Pat<(f64 fpimmneg0), (CHS_Fp64 (LD_Fp064))>, Requires<[FPStackf64]>;
|
|
def : Pat<(f64 fpimmneg1), (CHS_Fp64 (LD_Fp164))>, Requires<[FPStackf64]>;
|
|
def : Pat<(f80 fpimmneg0), (CHS_Fp80 (LD_Fp080))>;
|
|
def : Pat<(f80 fpimmneg1), (CHS_Fp80 (LD_Fp180))>;
|
|
|
|
// Used to conv. i64 to f64 since there isn't a SSE version.
|
|
def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>;
|
|
|
|
// Used to conv. between f80 and i64 for i64 atomic loads.
|
|
def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m80 addr:$src)>;
|
|
def : Pat<(X86fist64 RFP80:$src, addr:$op), (IST_Fp64m80 addr:$op, RFP80:$src)>;
|
|
|
|
// FP extensions map onto simple pseudo-value conversions if they are to/from
|
|
// the FP stack.
|
|
def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
|
|
Requires<[FPStackf32]>;
|
|
def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
|
|
Requires<[FPStackf32]>;
|
|
def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
|
|
Requires<[FPStackf64]>;
|
|
|
|
// FP truncations map onto simple pseudo-value conversions if they are to/from
|
|
// the FP stack. We have validated that only value-preserving truncations make
|
|
// it through isel.
|
|
def : Pat<(f32 (fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
|
|
Requires<[FPStackf32]>;
|
|
def : Pat<(f32 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
|
|
Requires<[FPStackf32]>;
|
|
def : Pat<(f64 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
|
|
Requires<[FPStackf64]>;
|