87 lines
2.9 KiB
TableGen
87 lines
2.9 KiB
TableGen
//===-- X86SchedPredicates.td - X86 Scheduling Predicates --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines scheduling predicate definitions that are common to
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// all X86 subtargets.
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//
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//===----------------------------------------------------------------------===//
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// A predicate used to identify dependency-breaking instructions that clear the
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// content of the destination register. Note that this predicate only checks if
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// input registers are the same. This predicate doesn't make any assumptions on
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// the expected instruction opcodes, because different processors may implement
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// different zero-idioms.
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def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>;
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// A predicate used to identify VPERM that have bits 3 and 7 of their mask set.
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// On some processors, these VPERM instructions are zero-idioms.
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def ZeroIdiomVPERMPredicate : CheckAll<[
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ZeroIdiomPredicate,
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CheckImmOperand<3, 0x88>
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]>;
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// A predicate used to check if a LEA instruction uses all three source
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// operands: base, index, and offset.
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def IsThreeOperandsLEAPredicate: CheckAll<[
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// isRegOperand(Base)
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CheckIsRegOperand<1>,
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CheckNot<CheckInvalidRegOperand<1>>,
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// isRegOperand(Index)
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CheckIsRegOperand<3>,
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CheckNot<CheckInvalidRegOperand<3>>,
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// hasLEAOffset(Offset)
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CheckAny<[
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CheckAll<[
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CheckIsImmOperand<4>,
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CheckNot<CheckZeroOperand<4>>
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]>,
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CheckNonPortable<"MI.getOperand(4).isGlobal()">
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]>
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]>;
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def LEACases : MCOpcodeSwitchCase<
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[LEA32r, LEA64r, LEA64_32r, LEA16r],
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MCReturnStatement<IsThreeOperandsLEAPredicate>
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>;
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// Used to generate the body of a TII member function.
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def IsThreeOperandsLEABody :
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MCOpcodeSwitchStatement<[LEACases], MCReturnStatement<FalsePred>>;
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// This predicate evaluates to true only if the input machine instruction is a
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// 3-operands LEA. Tablegen automatically generates a new method for it in
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// X86GenInstrInfo.
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def IsThreeOperandsLEAFn :
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TIIPredicate<"isThreeOperandsLEA", IsThreeOperandsLEABody>;
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// A predicate to check for COND_A and COND_BE CMOVs which have an extra uop
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// on recent Intel CPUs.
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def IsCMOVArr_Or_CMOVBErr : CheckAny<[
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CheckImmOperand_s<3, "X86::COND_A">,
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CheckImmOperand_s<3, "X86::COND_BE">
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]>;
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def IsCMOVArm_Or_CMOVBErm : CheckAny<[
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CheckImmOperand_s<7, "X86::COND_A">,
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CheckImmOperand_s<7, "X86::COND_BE">
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]>;
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// A predicate to check for COND_A and COND_BE SETCCs which have an extra uop
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// on recent Intel CPUs.
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def IsSETAr_Or_SETBEr : CheckAny<[
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CheckImmOperand_s<1, "X86::COND_A">,
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CheckImmOperand_s<1, "X86::COND_BE">
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]>;
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def IsSETAm_Or_SETBEm : CheckAny<[
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CheckImmOperand_s<5, "X86::COND_A">,
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CheckImmOperand_s<5, "X86::COND_BE">
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]>;
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