Simon Atanasyan bb36aea1d5 [mips] Support sigrie instruction ... The `sigrie` instruction signals a Reserved Instruction Exception. This patch adds support for assembling / disassembling the instruction. Differential Revision: http://reviews.llvm.org/D53861 llvm-svn: 346230		2018-11-06 14:37:24 +00:00
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invalid-mips1-wrong-error.s	[mips] Correct the predicates of the load/store (double)word for coprocessor 3.	2018-04-12 14:41:38 +00:00
invalid-mips1.s	…
invalid-mips2-wrong-error.s	…
invalid-mips2.s	…
invalid-mips4-wrong-error.s	…
invalid-mips4.s	…
invalid-mips5-wrong-error.s	[mips] Show an error if register number is out of range	2018-04-24 16:14:00 +00:00
invalid-mips5.s	…
invalid-mips32-wrong-error.s	…
invalid-mips32.s	…
invalid-mips32r2.s	…
invalid.s	[mips] Accept 32-bit offsets for lh and lhu commands	2018-05-10 16:01:18 +00:00
relocations.s	…
valid.s	[mips] Support sigrie instruction	2018-11-06 14:37:24 +00:00