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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 6c90a654bb [RISCV] Simplify some code in lowering vector int<->fp conversions. NFC 
Don't call EltVT.getSizeInBits() or SrcEltVT.getSizeInBits() a second
time. They are already in EltSize or SrcEltSize variables.

Refactor some comparisons to use multiply instead of division.
 		2022-03-23 12:09:05 -07:00
..
AsmParser [RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute 2022-03-24 00:48:52 +08:00
Disassembler [RISCV] add the MC layer support of Zfinx extension 2022-03-02 14:25:19 +08:00
MCTargetDesc [RISCV] Remove check and update test file in D121183 2022-03-24 00:48:52 +08:00
TargetInfo Fix shlib builds for all lib/Target/*/TargetInfo libs 2021-10-08 15:21:13 -07:00
CMakeLists.txt [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCV.h [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCV.td [RISCV] Add +experimental-zvfh extension to cover half types in vectors. 2022-03-17 10:04:02 -07:00
RISCVAsmPrinter.cpp [RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute 2022-03-24 00:48:52 +08:00
RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVCallingConv.td
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RISCVExpandAtomicPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp [RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes. 2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
RISCVFrameLowering.h Revert "[RISCV] Enable shrink wrap by default" 2022-02-12 19:04:12 +01:00
RISCVGatherScatterLowering.cpp [RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values. 2022-01-04 10:13:34 -08:00
RISCVISelDAGToDAG.cpp [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR 2022-03-22 07:47:21 -07:00
RISCVISelDAGToDAG.h [RISCV] Select unmasked RVV pseudos in a DAG post-process 2022-02-09 07:50:15 +00:00
RISCVISelLowering.cpp [RISCV] Simplify some code in lowering vector int<->fp conversions. NFC 2022-03-23 12:09:05 -07:00
RISCVISelLowering.h [RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32 2022-03-13 18:06:09 +08:00
RISCVInsertVSETVLI.cpp [RISCV] Support mask policy for RVV IR intrinsics. 2022-03-22 01:19:16 -07:00
RISCVInstrFormats.td [RISCV] Support mask policy for RVV IR intrinsics. 2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td [RISCV] Remove Zvamo Extention 2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove" 2022-02-17 17:27:37 +08:00
RISCVInstrInfo.h [MachineOutliner] NFC: Hide LRU-related stuff behind helper functions 2022-02-16 11:39:07 -08:00
RISCVInstrInfo.td [RISCV] Ensure PseudoLA* can be hoisted 2022-03-16 18:45:36 +00:00
RISCVInstrInfoA.td [RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage 2022-02-28 14:02:43 +08:00
RISCVInstrInfoC.td [llvm-tblgen][RISCV] Make llvm-tblgen RISCVCompressInstEmitter to be common infra across different targets 2021-11-18 11:14:27 +08:00
RISCVInstrInfoD.td [RISCV] Share PatFprFpr classes for F, D, and Zfh 2022-03-08 13:02:04 +08:00
RISCVInstrInfoF.td [RISCV] Share PatFprFpr classes for F, D, and Zfh 2022-03-08 13:02:04 +08:00
RISCVInstrInfoM.td [RISCV] Use MULHU for more division by constant cases. 2021-12-09 09:10:14 -08:00
RISCVInstrInfoV.td [TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc. 2022-03-22 10:14:43 -07:00
RISCVInstrInfoVPseudos.td [RISCV] Add policy operand for masked compare and vmsbf/vmsif/vmsof IR 2022-03-22 07:47:21 -07:00
RISCVInstrInfoVSDPatterns.td [RISCV] Fold store of vmv.f.s to a vse with VL=1. 2022-03-03 16:35:19 +08:00
RISCVInstrInfoVVLPatterns.td [RISCV] Add patterns for vnsrl.wi and vnsra.wi instructions 2022-03-17 07:22:32 +00:00
RISCVInstrInfoZb.td [RISCV] Move GORCIW/GREVIW formation to isel patterns. 2022-03-11 18:02:47 -08:00
RISCVInstrInfoZfh.td [RISCV] Share PatFprFpr classes for F, D, and Zfh 2022-03-08 13:02:04 +08:00
RISCVInstrInfoZk.td [RISCV] Adjust some comments. 2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp [Target] Remove redundant member initialization (NFC) 2022-01-06 22:01:44 -08:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp [NFC] Use Register instead of unsigned 2022-01-19 20:17:04 +08:00
RISCVMachineFunctionInfo.h
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RISCVMergeBaseOffset.cpp [NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments 2022-03-16 20:25:42 +08:00
RISCVRedundantCopyElimination.cpp [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass. 2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp [nfc][codegen] Move RegisterBank[Info].h under CodeGen 2022-03-01 21:53:25 -08:00
RISCVRegisterBankInfo.h [nfc][codegen] Move RegisterBank[Info].h under CodeGen 2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp Drop some more global std::maps. NFCI. 2022-03-06 13:28:29 +01:00
RISCVRegisterInfo.h [RISCV] Set CostPerUse to 1 iff RVC is enabled 2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td [RISCV] add the MC layer support of Zfinx extension 2022-03-02 14:25:19 +08:00
RISCVSExtWRemoval.cpp [RISCV] Add more sign-extending ops to MIR sext.w pass. 2022-03-18 18:21:17 +08:00
RISCVSchedRocket.td [RISCV] Add schedule class for Zbp extension and Zbr extension 2022-03-01 07:35:59 +00:00
RISCVSchedSiFive7.td [RISCV] Add schedule class for Zbp extension and Zbr extension 2022-03-01 07:35:59 +00:00
RISCVSchedule.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVScheduleB.td [RISCV] Add schedule class for Zbp extension and Zbr extension 2022-03-01 07:35:59 +00:00
RISCVScheduleV.td [RISCV] Add scheduling resources for V 2021-08-03 15:47:51 -05:00
RISCVSubtarget.cpp [RISCV] Support 'generic' as a valid CPU name. 2022-03-09 16:43:22 -08:00
RISCVSubtarget.h [RISCV] Add +experimental-zvfh extension to cover half types in vectors. 2022-03-17 10:04:02 -07:00
RISCVSystemOperands.td [RISCV] Initially support the K-extension instructions on the LLVM MC layer 2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp mark getTargetTransformInfo and getTargetIRAnalysis as const 2022-02-25 14:30:44 -05:00
RISCVTargetMachine.h mark getTargetTransformInfo and getTargetIRAnalysis as const 2022-02-25 14:30:44 -05:00
RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp Revert "Recommit "[SLP] Fix lookahead operand reordering for splat loads." attempt 2, fixed assertion crash." 2022-03-23 10:57:45 -07:00
RISCVTargetTransformInfo.h Revert "Recommit "[SLP] Fix lookahead operand reordering for splat loads." attempt 2, fixed assertion crash." 2022-03-23 10:57:45 -07:00