Simon Pilgrim 0c9c92ffc0 [X86][XOP] Tidyup VPHADD/VPHSUB unary horizontal ops default schedule class ... Based off Agner and AMD SoG tables, the XOP VPHADD/VPHSUB unary horizontal ops are as fast as basic arithmetic ops, not the slower SSSE3 binary horizontal add/sub ops. This also matches what the bdver2 model already lists. Noticed while investigating reduction add optimizations.		2022-03-03 12:07:48 +00:00
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Atom	[MCA][X86] Add missing zero-idioms test file coverage	2022-01-17 16:04:39 +00:00
Barcelona	[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs	2022-02-08 09:20:20 -08:00
BdVer2	[MCA] Switching from conservatively guessing which instructions are	2022-01-11 13:50:14 -08:00
Broadwell	[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs	2022-02-08 09:20:20 -08:00
BtVer2	[MCA] Switching from conservatively guessing which instructions are	2022-01-11 13:50:14 -08:00
Generic	[X86][XOP] Tidyup VPHADD/VPHSUB unary horizontal ops default schedule class	2022-03-03 12:07:48 +00:00
Haswell	[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs	2022-02-08 09:20:20 -08:00
IceLakeServer	[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs	2022-02-08 09:20:20 -08:00
SLM	[X86] Add some missing dependency-breaking zero idiom patterns to scheduler models	2022-01-19 11:29:33 +00:00
SandyBridge	[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs	2022-02-08 09:20:20 -08:00
SkylakeClient	[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs	2022-02-08 09:20:20 -08:00
SkylakeServer	[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUs	2022-02-08 09:20:20 -08:00
Znver1	[X86] Add some missing dependency-breaking zero idiom patterns to scheduler models	2022-01-19 11:29:33 +00:00
Znver2	[X86] Add some missing dependency-breaking zero idiom patterns to scheduler models	2022-01-19 11:29:33 +00:00
Znver3	[MCA][X86] Fix duplicated cvtsi2ss/cvtsi2sd i32 + i64 folded tests	2021-12-12 22:48:45 +00:00
barrier_output.s	[MCA] Switching from conservatively guessing which instructions are	2022-01-11 13:50:14 -08:00
bextr-read-after-ld.s	…
bzhi-read-after-ld.s	…
cpus.s	…
cv_fpo_directive_no_segfault.s	…
default-iterations.s	…
directives-handle-crlf.s	…
dispatch_width.s	…
fma3-read-after-ld-1.s	…
fma3-read-after-ld-2.s	…
in-order-cpu.s	[MCA] Remove the warning about experimental support for in-order CPU	2021-12-07 15:27:51 +03:00
intel-syntax.s	…
invalid-assembly-sequence.s	…
invalid-cpu.s	…
invalid-empty-file.s	…
lit.local.cfg	…
llvm-mca-markers-1.s	…
llvm-mca-markers-2.s	…
llvm-mca-markers-3.s	…
llvm-mca-markers-4.s	…
llvm-mca-markers-5.s	…
llvm-mca-markers-6.s	…
llvm-mca-markers-7.s	…
llvm-mca-markers-8.s	…
llvm-mca-markers-9.s	…
llvm-mca-markers-10.s	…
llvm-mca-markers-11.s	…
llvm-mca-markers-12.s	…
no-sched-model.s	…
option-all-stats-1.s	…
option-all-stats-2.s	…
option-all-views-1.s	…
option-all-views-2.s	…
option-no-stats-1.s	…
print-imm-hex-1.s	…
print-imm-hex-2.s	…
read-after-ld-1.s	…
read-after-ld-2.s	…
read-after-ld-3.s	…
register-file-statistics.s	…
scheduler-queue-usage.s	…
show-encoding.s	…
sqrt-rsqrt-rcp-memop.s	…
uop-queue.s	…
variable-blend-read-after-ld-1.s	…
variable-blend-read-after-ld-2.s	…