6eb8fc9244
Many of the x86 scheduler models are not accounting for their microarch's ability to handle dependency-breaking zero idioms (pxor xmm0,xmm0 etc.), which is causing some notable differences when comparing llvm-mca reports to iaca, uops.info etc. These are based on the Intel AoMs and Agner's docs which list the instructions handled on each cpu model - there may be more, although tbh the xor/pxor/xorps/xorpd are by far the most commonly encountered. Once this is in place we also need to review missing support for 'allones' idioms and reg-reg move elimination, but this needs fixing first. @lebedev.ri The Barcelona test changes are due to the cpu still being tagged as using the SandyBridge model, if/when you get back to D63628 these will need to be addressed. Based on an original patch by @andreadb (Andrea Di Biagio) Differential Revision: https://reviews.llvm.org/D117497 |
||
|---|---|---|
| .. | ||
| resources-aes.s | ||
| resources-cmov.s | ||
| resources-cmpxchg.s | ||
| resources-lea.s | ||
| resources-mmx.s | ||
| resources-movbe.s | ||
| resources-pclmul.s | ||
| resources-popcnt.s | ||
| resources-prefetchw.s | ||
| resources-rdrand.s | ||
| resources-rdseed.s | ||
| resources-sse1.s | ||
| resources-sse2.s | ||
| resources-sse3.s | ||
| resources-sse41.s | ||
| resources-sse42.s | ||
| resources-ssse3.s | ||
| resources-x86_32.s | ||
| resources-x86_64.s | ||
| resources-x87.s | ||
| zero-idioms.s | ||