llvm-project/llvm/test/CodeGen/RISCV/bittest.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefix=RV64I
; RUN: llc -mtriple=riscv64 -mattr=+zbs -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefix=RV64ZBS

define signext i32 @bittest_7_i32(i32 signext %a) nounwind {
; RV64I-LABEL: bittest_7_i32:
; RV64I:       # %bb.0:
; RV64I-NEXT:    andi a0, a0, 128
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_7_i32:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    andi a0, a0, 128
; RV64ZBS-NEXT:    seqz a0, a0
; RV64ZBS-NEXT:    ret
  %shr = lshr i32 %a, 7
  %not = xor i32 %shr, -1
  %and = and i32 %not, 1
  ret i32 %and
}

define signext i32 @bittest_10_i32(i32 signext %a) nounwind {
; RV64I-LABEL: bittest_10_i32:
; RV64I:       # %bb.0:
; RV64I-NEXT:    andi a0, a0, 1024
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_10_i32:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    andi a0, a0, 1024
; RV64ZBS-NEXT:    seqz a0, a0
; RV64ZBS-NEXT:    ret
  %shr = lshr i32 %a, 10
  %not = xor i32 %shr, -1
  %and = and i32 %not, 1
  ret i32 %and
}

define signext i32 @bittest_11_i32(i32 signext %a) nounwind {
; RV64I-LABEL: bittest_11_i32:
; RV64I:       # %bb.0:
; RV64I-NEXT:    srli a0, a0, 11
; RV64I-NEXT:    not a0, a0
; RV64I-NEXT:    andi a0, a0, 1
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_11_i32:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    bexti a0, a0, 11
; RV64ZBS-NEXT:    xori a0, a0, 1
; RV64ZBS-NEXT:    ret
  %shr = lshr i32 %a, 11
  %not = xor i32 %shr, -1
  %and = and i32 %not, 1
  ret i32 %and
}

define signext i32 @bittest_31_i32(i32 signext %a) nounwind {
; RV64I-LABEL: bittest_31_i32:
; RV64I:       # %bb.0:
; RV64I-NEXT:    not a0, a0
; RV64I-NEXT:    srliw a0, a0, 31
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_31_i32:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    not a0, a0
; RV64ZBS-NEXT:    srliw a0, a0, 31
; RV64ZBS-NEXT:    ret
  %shr = lshr i32 %a, 31
  %not = xor i32 %shr, -1
  %and = and i32 %not, 1
  ret i32 %and
}

define i64 @bittest_7_i64(i64 %a) nounwind {
; RV64I-LABEL: bittest_7_i64:
; RV64I:       # %bb.0:
; RV64I-NEXT:    andi a0, a0, 128
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_7_i64:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    andi a0, a0, 128
; RV64ZBS-NEXT:    seqz a0, a0
; RV64ZBS-NEXT:    ret
  %shr = lshr i64 %a, 7
  %not = xor i64 %shr, -1
  %and = and i64 %not, 1
  ret i64 %and
}

define i64 @bittest_10_i64(i64 %a) nounwind {
; RV64I-LABEL: bittest_10_i64:
; RV64I:       # %bb.0:
; RV64I-NEXT:    andi a0, a0, 1024
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_10_i64:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    andi a0, a0, 1024
; RV64ZBS-NEXT:    seqz a0, a0
; RV64ZBS-NEXT:    ret
  %shr = lshr i64 %a, 10
  %not = xor i64 %shr, -1
  %and = and i64 %not, 1
  ret i64 %and
}

define i64 @bittest_11_i64(i64 %a) nounwind {
; RV64I-LABEL: bittest_11_i64:
; RV64I:       # %bb.0:
; RV64I-NEXT:    srli a0, a0, 11
; RV64I-NEXT:    not a0, a0
; RV64I-NEXT:    andi a0, a0, 1
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_11_i64:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    bexti a0, a0, 11
; RV64ZBS-NEXT:    xori a0, a0, 1
; RV64ZBS-NEXT:    ret
  %shr = lshr i64 %a, 11
  %not = xor i64 %shr, -1
  %and = and i64 %not, 1
  ret i64 %and
}

define i64 @bittest_31_i64(i64 %a) nounwind {
; RV64I-LABEL: bittest_31_i64:
; RV64I:       # %bb.0:
; RV64I-NEXT:    srli a0, a0, 31
; RV64I-NEXT:    not a0, a0
; RV64I-NEXT:    andi a0, a0, 1
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_31_i64:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    bexti a0, a0, 31
; RV64ZBS-NEXT:    xori a0, a0, 1
; RV64ZBS-NEXT:    ret
  %shr = lshr i64 %a, 31
  %not = xor i64 %shr, -1
  %and = and i64 %not, 1
  ret i64 %and
}

define i64 @bittest_32_i64(i64 %a) nounwind {
; RV64I-LABEL: bittest_32_i64:
; RV64I:       # %bb.0:
; RV64I-NEXT:    srli a0, a0, 32
; RV64I-NEXT:    not a0, a0
; RV64I-NEXT:    andi a0, a0, 1
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_32_i64:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    bexti a0, a0, 32
; RV64ZBS-NEXT:    xori a0, a0, 1
; RV64ZBS-NEXT:    ret
  %shr = lshr i64 %a, 32
  %not = xor i64 %shr, -1
  %and = and i64 %not, 1
  ret i64 %and
}

define i64 @bittest_63_i64(i64 %a) nounwind {
; RV64I-LABEL: bittest_63_i64:
; RV64I:       # %bb.0:
; RV64I-NEXT:    not a0, a0
; RV64I-NEXT:    srli a0, a0, 63
; RV64I-NEXT:    ret
;
; RV64ZBS-LABEL: bittest_63_i64:
; RV64ZBS:       # %bb.0:
; RV64ZBS-NEXT:    not a0, a0
; RV64ZBS-NEXT:    srli a0, a0, 63
; RV64ZBS-NEXT:    ret
  %shr = lshr i64 %a, 63
  %not = xor i64 %shr, -1
  %and = and i64 %not, 1
  ret i64 %and
}