llvm-project/llvm/test/CodeGen/RISCV/i64-icmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefix=RV64I

define i64 @icmp_eq(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_eq:
; RV64I:       # %bb.0:
; RV64I-NEXT:    xor a0, a0, a1
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp eq i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_eq_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi a0, a0, -42
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp eq i64 %a, 42
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_eq_constant_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_2049:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1
; RV64I-NEXT:    addiw a1, a1, -2047
; RV64I-NEXT:    xor a0, a0, a1
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp eq i64 %a, 2049
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_eq_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi a0, a0, -2048
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp eq i64 %a, 2048
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_eq_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_neg_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, -2048
; RV64I-NEXT:    xor a0, a0, a1
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp eq i64 %a, -2048
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_eq_constant_neg_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_eq_constant_neg_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi a0, a0, 2047
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp eq i64 %a, -2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_eqz(i64 %a) nounwind {
; RV64I-LABEL: icmp_eqz:
; RV64I:       # %bb.0:
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp eq i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ne(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ne:
; RV64I:       # %bb.0:
; RV64I-NEXT:    xor a0, a0, a1
; RV64I-NEXT:    snez a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ne i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ne_constant(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi a0, a0, -42
; RV64I-NEXT:    snez a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ne i64 %a, 42
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ne_constant_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_2049:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1
; RV64I-NEXT:    addiw a1, a1, -2047
; RV64I-NEXT:    xor a0, a0, a1
; RV64I-NEXT:    snez a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ne i64 %a, 2049
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ne_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi a0, a0, -2048
; RV64I-NEXT:    snez a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ne i64 %a, 2048
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ne_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_neg_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, -2048
; RV64I-NEXT:    xor a0, a0, a1
; RV64I-NEXT:    snez a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ne i64 %a, -2048
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ne_constant_neg_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_ne_constant_neg_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addi a0, a0, 2047
; RV64I-NEXT:    snez a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ne i64 %a, -2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_nez(i64 %a) nounwind {
; RV64I-LABEL: icmp_nez:
; RV64I:       # %bb.0:
; RV64I-NEXT:    snez a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ne i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ugt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ugt:
; RV64I:       # %bb.0:
; RV64I-NEXT:    sltu a0, a1, a0
; RV64I-NEXT:    ret
  %1 = icmp ugt i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ugt_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_zero:
; RV64I:       # %bb.0:
; RV64I-NEXT:    snez a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ugt i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ugt_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, 2047
; RV64I-NEXT:    sltu a0, a1, a0
; RV64I-NEXT:    ret
  %1 = icmp ugt i64 %a, 2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ugt_constant_2046(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_2046:
; RV64I:       # %bb.0:
; RV64I-NEXT:    sltiu a0, a0, 2047
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp ugt i64 %a, 2046
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ugt_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_neg_2049:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1046527
; RV64I-NEXT:    slli a1, a1, 20
; RV64I-NEXT:    srli a1, a1, 32
; RV64I-NEXT:    sltu a0, a1, a0
; RV64I-NEXT:    ret
; 4294965247 signed extend is -2049
  %1 = icmp ugt i64 %a, 4294965247
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ugt_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ugt_constant_neg_2050:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, -1025
; RV64I-NEXT:    slli a1, a1, 33
; RV64I-NEXT:    srli a1, a1, 32
; RV64I-NEXT:    sltu a0, a1, a0
; RV64I-NEXT:    ret
; 4294965246 signed extend is -2050
  %1 = icmp ugt i64 %a, 4294965246
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_uge(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_uge:
; RV64I:       # %bb.0:
; RV64I-NEXT:    sltu a0, a0, a1
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp uge i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_uge_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_zero:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a0, 1
; RV64I-NEXT:    ret
  %1 = icmp uge i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_uge_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    sltiu a0, a0, 2047
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp uge i64 %a, 2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_uge_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, 2047
; RV64I-NEXT:    sltu a0, a1, a0
; RV64I-NEXT:    ret
  %1 = icmp uge i64 %a, 2048
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_uge_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_neg_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1046527
; RV64I-NEXT:    slli a1, a1, 20
; RV64I-NEXT:    srli a1, a1, 32
; RV64I-NEXT:    sltu a0, a1, a0
; RV64I-NEXT:    ret
; 4294965248 signed extend is -2048
  %1 = icmp uge i64 %a, 4294965248
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_uge_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_uge_constant_neg_2049:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, -1025
; RV64I-NEXT:    slli a1, a1, 33
; RV64I-NEXT:    srli a1, a1, 32
; RV64I-NEXT:    sltu a0, a1, a0
; RV64I-NEXT:    ret
; 4294965247 signed extend is -2049
  %1 = icmp uge i64 %a, 4294965247
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ult(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ult:
; RV64I:       # %bb.0:
; RV64I-NEXT:    sltu a0, a0, a1
; RV64I-NEXT:    ret
  %1 = icmp ult i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ult_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_zero:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a0, 0
; RV64I-NEXT:    ret
  %1 = icmp ult i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ult_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    sltiu a0, a0, 2047
; RV64I-NEXT:    ret
  %1 = icmp ult i64 %a, 2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ult_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    srli a0, a0, 11
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ult i64 %a, 2048
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ult_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_neg_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, 1
; RV64I-NEXT:    slli a1, a1, 32
; RV64I-NEXT:    addi a1, a1, -2048
; RV64I-NEXT:    sltu a0, a0, a1
; RV64I-NEXT:    ret
; 4294965248 signed extend is -2048
  %1 = icmp ult i64 %a, 4294965248
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ult_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ult_constant_neg_2049:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1046527
; RV64I-NEXT:    slli a1, a1, 20
; RV64I-NEXT:    srli a1, a1, 32
; RV64I-NEXT:    sltu a0, a0, a1
; RV64I-NEXT:    ret
; 4294965247 signed extend is -2049
  %1 = icmp ult i64 %a, 4294965247
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ule(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_ule:
; RV64I:       # %bb.0:
; RV64I-NEXT:    sltu a0, a1, a0
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp ule i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ule_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_zero:
; RV64I:       # %bb.0:
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ule i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ule_constant_2046(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_2046:
; RV64I:       # %bb.0:
; RV64I-NEXT:    sltiu a0, a0, 2047
; RV64I-NEXT:    ret
  %1 = icmp ule i64 %a, 2046
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ule_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    srli a0, a0, 11
; RV64I-NEXT:    seqz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp ule i64 %a, 2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ule_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_neg_2049:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, 1
; RV64I-NEXT:    slli a1, a1, 32
; RV64I-NEXT:    addi a1, a1, -2048
; RV64I-NEXT:    sltu a0, a0, a1
; RV64I-NEXT:    ret
; 4294965247 signed extend is -2049
  %1 = icmp ule i64 %a, 4294965247
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_ule_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_ule_constant_neg_2050:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1046527
; RV64I-NEXT:    slli a1, a1, 20
; RV64I-NEXT:    srli a1, a1, 32
; RV64I-NEXT:    sltu a0, a0, a1
; RV64I-NEXT:    ret
; 4294965246 signed extend is -2050
  %1 = icmp ule i64 %a, 4294965246
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sgt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_sgt:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slt a0, a1, a0
; RV64I-NEXT:    ret
  %1 = icmp sgt i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sgt_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_zero:
; RV64I:       # %bb.0:
; RV64I-NEXT:    sgtz a0, a0
; RV64I-NEXT:    ret
  %1 = icmp sgt i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sgt_constant_2046(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_2046:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slti a0, a0, 2047
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp sgt i64 %a, 2046
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sgt_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, 2047
; RV64I-NEXT:    slt a0, a1, a0
; RV64I-NEXT:    ret
  %1 = icmp sgt i64 %a, 2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sgt_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_neg_2049:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slti a0, a0, -2048
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp sgt i64 %a, -2049
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sgt_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_sgt_constant_neg_2050:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1048575
; RV64I-NEXT:    addiw a1, a1, 2046
; RV64I-NEXT:    slt a0, a1, a0
; RV64I-NEXT:    ret
  %1 = icmp sgt i64 %a, -2050
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sge(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_sge:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slt a0, a0, a1
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp sge i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sge_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_zero:
; RV64I:       # %bb.0:
; RV64I-NEXT:    not a0, a0
; RV64I-NEXT:    srli a0, a0, 63
; RV64I-NEXT:    ret
  %1 = icmp sge i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sge_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slti a0, a0, 2047
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp sge i64 %a, 2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sge_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    li a1, 2047
; RV64I-NEXT:    slt a0, a1, a0
; RV64I-NEXT:    ret
  %1 = icmp sge i64 %a, 2048
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sge_constant_neg_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_neg_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slti a0, a0, -2047
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp sge i64 %a, -2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sge_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_sge_constant_neg_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    not a0, a0
; RV64I-NEXT:    srli a0, a0, 63
; RV64I-NEXT:    ret
  %1 = icmp sge i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_slt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_slt:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slt a0, a0, a1
; RV64I-NEXT:    ret
  %1 = icmp slt i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_slt_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_zero:
; RV64I:       # %bb.0:
; RV64I-NEXT:    srli a0, a0, 63
; RV64I-NEXT:    ret
  %1 = icmp slt i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_slt_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slti a0, a0, 2047
; RV64I-NEXT:    ret
  %1 = icmp slt i64 %a, 2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_slt_constant_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1
; RV64I-NEXT:    addiw a1, a1, -2048
; RV64I-NEXT:    slt a0, a0, a1
; RV64I-NEXT:    ret
  %1 = icmp slt i64 %a, 2048
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_slt_constant_neg_2048(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_neg_2048:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slti a0, a0, -2048
; RV64I-NEXT:    ret
  %1 = icmp slt i64 %a, -2048
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_slt_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_slt_constant_neg_2049:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1048575
; RV64I-NEXT:    addiw a1, a1, 2047
; RV64I-NEXT:    slt a0, a0, a1
; RV64I-NEXT:    ret
  %1 = icmp slt i64 %a, -2049
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sle(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: icmp_sle:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slt a0, a1, a0
; RV64I-NEXT:    xori a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp sle i64 %a, %b
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sle_constant_zero(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_zero:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slti a0, a0, 1
; RV64I-NEXT:    ret
  %1 = icmp sle i64 %a, 0
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sle_constant_2046(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_2046:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slti a0, a0, 2047
; RV64I-NEXT:    ret
  %1 = icmp sle i64 %a, 2046
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sle_constant_2047(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_2047:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1
; RV64I-NEXT:    addiw a1, a1, -2048
; RV64I-NEXT:    slt a0, a0, a1
; RV64I-NEXT:    ret
  %1 = icmp sle i64 %a, 2047
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sle_constant_neg_2049(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_neg_2049:
; RV64I:       # %bb.0:
; RV64I-NEXT:    slti a0, a0, -2048
; RV64I-NEXT:    ret
  %1 = icmp sle i64 %a, -2049
  %2 = zext i1 %1 to i64
  ret i64 %2
}

define i64 @icmp_sle_constant_neg_2050(i64 %a) nounwind {
; RV64I-LABEL: icmp_sle_constant_neg_2050:
; RV64I:       # %bb.0:
; RV64I-NEXT:    lui a1, 1048575
; RV64I-NEXT:    addiw a1, a1, 2047
; RV64I-NEXT:    slt a0, a0, a1
; RV64I-NEXT:    ret
  %1 = icmp sle i64 %a, -2050
  %2 = zext i1 %1 to i64
  ret i64 %2
}