llvm-project/llvm/test/MC/Disassembler
Stefan Pintilie 2e55bc9f3c [PowerPC] Set the special DSCR with a compiler option.
Add a compiler option and the instructions required to set the
special Data Stream Control Register (DSCR). The special register will
not be set by default.

Original patch by: Muhammad Usman

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D117013
2022-03-31 14:06:30 -05:00
..
AArch64 [AArch64] Move FeatureSpecRestrict into core 8.0-R architecture. 2022-03-07 15:55:08 +00:00
AMDGPU [AMDGPU] Support gfx940 smfmac instructions 2022-03-24 12:40:42 -07:00
ARC [ARC] Add ADC (addition with carry) and SBC (subtraction with carry) instructions 2021-08-25 07:46:15 -07:00
ARM [ARM] Implement PAC return address signing mechanism for PACBTI-M 2021-12-07 10:15:19 +00:00
Hexagon
Lanai
M68k [M68k] Adopt VarLenCodeEmitter for bits instructions 2022-02-17 14:16:19 -08:00
MSP430
Mips
PowerPC [PowerPC] Set the special DSCR with a compiler option. 2022-03-31 14:06:30 -05:00
RISCV [RISCV] Add support for Zihintpause extention 2022-02-03 20:55:47 +08:00
Sparc
SystemZ [SystemZ] Add support for new cpu architecture - arch14 2021-07-26 16:57:28 +02:00
WebAssembly [WebAssembly] Update v128.any_true 2021-04-11 11:13:16 -07:00
X86 [MC][X86] Ensure all opcode tests are sorted by instruction name 2022-03-30 11:08:11 +01:00
XCore