llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex
David Green 61b616755a Partially revert "[SchedModels][CortexA55] Add ASIMD integer instructions"
The Cortex-A55 scheduling model is used for -mcpu=generic, meaning it
can have a wider effect than just the A55. The changes to the A55
scheduling model seems to have caused performance regressions on
Cortex-A510 device which have latencies closer to the original and
different forwarding paths.

This partially reverts the changes from D117003, at least until we can
do something to improve Cortex-A510. According to my results, this
improves the A510 results without altering the A55 very much.
2022-02-28 10:58:52 +00:00
..
IPC
A53-carry-over.s
A55-add-sequence.s
A55-all-stats.s
A55-all-views.s
A55-basic-instructions.s [SchedModels][CortexA55] Fix scheduling of FP loads 2022-01-10 10:14:45 +03:00
A55-in-order-retire.s
A55-load-readadv.s [SchedModels][CortexA55] Fix scheduling of FP loads 2022-01-10 10:14:45 +03:00
A55-load-store-alias.s
A55-load-store-noalias.s [MCA] Switching from conservatively guessing which instructions are 2022-01-11 13:50:14 -08:00
A55-neon-instructions.s Partially revert "[SchedModels][CortexA55] Add ASIMD integer instructions" 2022-02-28 10:58:52 +00:00
A55-out-of-order-retire.s
A55-store-readadv.s [AArch64] Correct store ReadAdrBase operand 2021-08-23 21:07:55 +01:00
direct-branch.s
forwarding-A57.s
in-order-bottleneck-analysis.s
shifted-register.s