142 lines
4.3 KiB
LLVM
142 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s
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define void @i24_or(i24* %a) {
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; CHECK-LABEL: i24_or:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: movzbl 2(%rdi), %ecx
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; CHECK-NEXT: movb %cl, 2(%rdi)
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; CHECK-NEXT: shll $16, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: orl $384, %ecx # imm = 0x180
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; CHECK-NEXT: movw %cx, (%rdi)
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; CHECK-NEXT: retq
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%aa = load i24, i24* %a, align 1
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%b = or i24 %aa, 384
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store i24 %b, i24* %a, align 1
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ret void
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}
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define void @i24_and_or(i24* %a) {
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; CHECK-LABEL: i24_and_or:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl (%rdi), %eax
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; CHECK-NEXT: movzbl 2(%rdi), %ecx
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; CHECK-NEXT: movb %cl, 2(%rdi)
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; CHECK-NEXT: shll $16, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: orl $384, %ecx # imm = 0x180
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; CHECK-NEXT: andl $16777088, %ecx # imm = 0xFFFF80
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; CHECK-NEXT: movw %cx, (%rdi)
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; CHECK-NEXT: retq
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%b = load i24, i24* %a, align 1
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%c = and i24 %b, -128
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%d = or i24 %c, 384
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store i24 %d, i24* %a, align 1
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ret void
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}
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define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
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; CHECK-LABEL: i24_insert_bit:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %sil, %eax
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; CHECK-NEXT: movzwl (%rdi), %ecx
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; CHECK-NEXT: movzbl 2(%rdi), %edx
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; CHECK-NEXT: movb %dl, 2(%rdi)
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; CHECK-NEXT: shll $16, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: shll $13, %eax
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; CHECK-NEXT: andl $16769023, %edx # imm = 0xFFDFFF
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; CHECK-NEXT: orl %eax, %edx
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; CHECK-NEXT: movw %dx, (%rdi)
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; CHECK-NEXT: retq
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%extbit = zext i1 %bit to i24
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%b = load i24, i24* %a, align 1
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%extbit.shl = shl nuw nsw i24 %extbit, 13
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%c = and i24 %b, -8193
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%d = or i24 %c, %extbit.shl
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store i24 %d, i24* %a, align 1
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ret void
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}
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define void @i56_or(i56* %a) {
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; CHECK-LABEL: i56_or:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl 4(%rdi), %eax
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; CHECK-NEXT: movzbl 6(%rdi), %ecx
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; CHECK-NEXT: movl (%rdi), %edx
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; CHECK-NEXT: movb %cl, 6(%rdi)
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; CHECK-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
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; CHECK-NEXT: shll $16, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: shlq $32, %rcx
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; CHECK-NEXT: orq %rcx, %rdx
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; CHECK-NEXT: orq $384, %rdx # imm = 0x180
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; CHECK-NEXT: movl %edx, (%rdi)
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; CHECK-NEXT: shrq $32, %rdx
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; CHECK-NEXT: movw %dx, 4(%rdi)
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; CHECK-NEXT: retq
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%aa = load i56, i56* %a, align 1
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%b = or i56 %aa, 384
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store i56 %b, i56* %a, align 1
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ret void
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}
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define void @i56_and_or(i56* %a) {
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; CHECK-LABEL: i56_and_or:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzwl 4(%rdi), %eax
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; CHECK-NEXT: movzbl 6(%rdi), %ecx
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; CHECK-NEXT: movl (%rdi), %edx
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; CHECK-NEXT: movb %cl, 6(%rdi)
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; CHECK-NEXT: # kill: %ECX<def> %ECX<kill> %RCX<kill> %RCX<def>
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; CHECK-NEXT: shll $16, %ecx
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; CHECK-NEXT: orl %eax, %ecx
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; CHECK-NEXT: shlq $32, %rcx
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; CHECK-NEXT: orq %rcx, %rdx
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; CHECK-NEXT: orq $384, %rdx # imm = 0x180
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; CHECK-NEXT: movabsq $72057594037927808, %rax # imm = 0xFFFFFFFFFFFF80
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; CHECK-NEXT: andq %rdx, %rax
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; CHECK-NEXT: movl %eax, (%rdi)
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; CHECK-NEXT: shrq $32, %rax
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; CHECK-NEXT: movw %ax, 4(%rdi)
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; CHECK-NEXT: retq
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%b = load i56, i56* %a, align 1
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%c = and i56 %b, -128
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%d = or i56 %c, 384
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store i56 %d, i56* %a, align 1
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ret void
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}
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define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
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; CHECK-LABEL: i56_insert_bit:
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; CHECK: # BB#0:
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; CHECK-NEXT: movzbl %sil, %eax
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; CHECK-NEXT: movzwl 4(%rdi), %ecx
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; CHECK-NEXT: movzbl 6(%rdi), %edx
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; CHECK-NEXT: movl (%rdi), %esi
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; CHECK-NEXT: movb %dl, 6(%rdi)
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; CHECK-NEXT: # kill: %EDX<def> %EDX<kill> %RDX<kill> %RDX<def>
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; CHECK-NEXT: shll $16, %edx
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; CHECK-NEXT: orl %ecx, %edx
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; CHECK-NEXT: shlq $32, %rdx
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; CHECK-NEXT: orq %rdx, %rsi
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; CHECK-NEXT: shlq $13, %rax
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; CHECK-NEXT: movabsq $72057594037919743, %rcx # imm = 0xFFFFFFFFFFDFFF
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; CHECK-NEXT: andq %rsi, %rcx
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; CHECK-NEXT: orq %rax, %rcx
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; CHECK-NEXT: movl %ecx, (%rdi)
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; CHECK-NEXT: shrq $32, %rcx
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; CHECK-NEXT: movw %cx, 4(%rdi)
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; CHECK-NEXT: retq
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%extbit = zext i1 %bit to i56
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%b = load i56, i56* %a, align 1
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%extbit.shl = shl nuw nsw i56 %extbit, 13
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%c = and i56 %b, -8193
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%d = or i56 %c, %extbit.shl
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store i56 %d, i56* %a, align 1
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ret void
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}
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